source: rtems/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_flash.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "" files.

Update #3254.

  • Property mode set to 100755
File size: 3.9 KB
2 * Copyright (c) 2013 Chris Nott.  All rights reserved.
3 *
4 *  Virtual Logic
5 *  21-25 King St.
6 *  Rockdale NSW 2216
7 *  Australia
8 *  <>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 *
13 */
18#include <bsp/utility.h>
20struct stm32f4_flash_s {
22  uint32_t acr;   // Access and control register
23#define STM32F4_FLASH_ACR_DCRST   BSP_BIT32(12) // Data cache reset
24#define STM32F4_FLASH_ACR_ICRST   BSP_BIT32(11) // Instruction cache reset
25#define STM32F4_FLASH_ACR_DCEN    BSP_BIT32(10) // Data cache enable
26#define STM32F4_FLASH_ACR_ICEN    BSP_BIT32(9)  // Instruction cache enable
27#define STM32F4_FLASH_ACR_PRFTEN  BSP_BIT32(8)  // Prefetch enable
28#define STM32F4_FLASH_ACR_LATENCY(val)  BSP_FLD32(val, 0, 2)  // Flash access latency
29#define STM32F4_FLASH_ACR_LATENCY_GET(reg)  BSP_FLD32GET(reg, 0, 2)
30#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
32  uint32_t keyr;  // Key register
33#define STM32F4_FLASH_KEYR_KEY1 0x45670123
34#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB
36  uint32_t optkeyr; // Option key register
37#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B
40  uint32_t sr;    // Status register
41#define STM32F4_FLASH_SR_BSY    BSP_BIT32(16) // Busy
42#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7)  // Programming sequence error
43#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6)  // Programming parallelism error
44#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5)  // Programming alignment error
45#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4)  // Write protection error
46#define STM32F4_FLASH_SR_OPERR  BSP_BIT32(1)  // Operation error
47#define STM32F4_FLASH_SR_EOP    BSP_BIT32(0)  // End of operation
49  uint32_t cr;    // Control register
50#define STM32F4_FLASH_CR_LOCK   BSP_BIT32(31) // Lock
51#define STM32F4_FLASH_CR_ERRIE  BSP_BIT32(25) // Error interrupt enable
52#define STM32F4_FLASH_CR_EOPIE  BSP_BIT32(24) // End of operation interrupt enable
53#define STM32F4_FLASH_CR_STRT   BSP_BIT32(16) // Start
54#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9)  // Program size
55#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9)
56#define STM32F4_FLASH_CR_PSIZE_SET(reg, val)  BSP_FLD32SET(reg, val, 8, 9)
57#define STM32F4_FLASH_CR_SNB  BSP_FLD32(val, 3, 6)  // Sector number
58#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6)
59#define STM32F4_FLASH_CR_SNB_SET(reg, val)  BSP_FLD32SET(reg, val, 3, 6)
60#define STM32F4_FLASH_CR_MER    BSP_BIT32(2)  // Mass erase
61#define STM32F4_FLASH_CR_SER    BSP_BIT32(1)  // Sector erase
62#define STM32F4_FLASH_CR_PG     BSP_BIT32(0)  // Programming
64  uint32_t optcr;   // Option control register
65#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27)  // Not write protect
66#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27)
67#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val)  BSP_FLD32SET(reg, val, 16, 27)
68#define STM32F4_FLASH_OPTCR_RDP(val)  BSP_FLD32(val, 8, 15) // Read protect
69#define STM32F4_FLASH_OPTCR_RDP_GET(reg)  BSP_FLD32GET(reg, 8, 15)
70#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
71#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7)  // User option bytes
72#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7)
73#define STM32F4_FLASH_OPTCR_USER_SET(reg, val)  BSP_FLD32SET(reg, val, 5, 7)
74#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val)  BSP_FLD32(val, 2, 3)  // BOR reset level
75#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg)  BSP_FLD32GET(reg, 2, 3)
76#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3)
77#define STM32F4_FLASH_CR_OPTSTRT  BSP_BIT32(1)  // Option start
78#define STM32F4_FLASH_CR_OPTLOCK  BSP_BIT32(0)  // Option lock
80} __attribute__ ((packed));
81typedef struct stm32f4_flash_s stm32f4_flash;
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