Last change
on this file since cd5573c was
cd5573c,
checked in by Sebastian Huber <sebastian.huber@…>, on 06/19/21 at 10:40:57
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bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNT
Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT.
After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be
removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The
BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no
interrupt vector at all. Using COUNT instead of MAX may avoid some
interpretation issues, for example is the maximum value a valid vector number
or not.
Update #3269.
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Property mode set to
100644
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File size:
2.7 KB
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1 | /* irq.h |
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2 | * |
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3 | * Copyright (c) 2010 embedded brains GmbH. |
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4 | * |
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5 | * CopyRight (C) 2000 Canon Research France SA. |
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6 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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7 | * |
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8 | * Common file, merged from s3c2400/irq/irq.h and s3c2410/irq/irq.h |
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9 | */ |
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10 | |
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11 | #ifndef _IRQ_H_ |
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12 | #define _IRQ_H_ |
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13 | |
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14 | #include <rtems.h> |
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15 | #include <rtems/irq.h> |
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16 | #include <rtems/irq-extension.h> |
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17 | |
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18 | #include <s3c24xx.h> |
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19 | |
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20 | #ifdef CPU_S3C2400 |
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21 | /* possible interrupt sources */ |
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22 | #define BSP_EINT0 0 |
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23 | #define BSP_EINT1 1 |
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24 | #define BSP_EINT2 2 |
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25 | #define BSP_EINT3 3 |
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26 | #define BSP_EINT4 4 |
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27 | #define BSP_EINT5 5 |
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28 | #define BSP_EINT6 6 |
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29 | #define BSP_EINT7 7 |
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30 | #define BSP_INT_TICK 8 |
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31 | #define BSP_INT_WDT 9 |
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32 | #define BSP_INT_TIMER0 10 |
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33 | #define BSP_INT_TIMER1 11 |
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34 | #define BSP_INT_TIMER2 12 |
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35 | #define BSP_INT_TIMER3 13 |
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36 | #define BSP_INT_TIMER4 14 |
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37 | #define BSP_INT_UERR01 15 |
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38 | #define _res0 16 |
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39 | #define BSP_INT_DMA0 17 |
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40 | #define BSP_INT_DMA1 18 |
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41 | #define BSP_INT_DMA2 19 |
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42 | #define BSP_INT_DMA3 20 |
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43 | #define BSP_INT_MMC 21 |
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44 | #define BSP_INT_SPI 22 |
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45 | #define BSP_INT_URXD0 23 |
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46 | #define BSP_INT_URXD1 24 |
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47 | #define BSP_INT_USBD 25 |
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48 | #define BSP_INT_USBH 26 |
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49 | #define BSP_INT_IIC 27 |
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50 | #define BSP_INT_UTXD0 28 |
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51 | #define BSP_INT_UTXD1 29 |
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52 | #define BSP_INT_RTC 30 |
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53 | #define BSP_INT_ADC 31 |
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54 | #define BSP_MAX_INT 32 |
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55 | |
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56 | #elif defined CPU_S3C2410 |
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57 | /* possible interrupt sources */ |
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58 | #define BSP_EINT0 0 |
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59 | #define BSP_EINT1 1 |
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60 | #define BSP_EINT2 2 |
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61 | #define BSP_EINT3 3 |
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62 | #define BSP_EINT4_7 4 |
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63 | #define BSP_EINT8_23 5 |
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64 | #define BSP_nBATT_FLT 7 |
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65 | #define BSP_INT_TICK 8 |
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66 | #define BSP_INT_WDT 9 |
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67 | #define BSP_INT_TIMER0 10 |
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68 | #define BSP_INT_TIMER1 11 |
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69 | #define BSP_INT_TIMER2 12 |
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70 | #define BSP_INT_TIMER3 13 |
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71 | #define BSP_INT_TIMER4 14 |
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72 | #define BSP_INT_UART2 15 |
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73 | #define BSP_INT_LCD 16 |
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74 | #define BSP_INT_DMA0 17 |
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75 | #define BSP_INT_DMA1 18 |
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76 | #define BSP_INT_DMA2 19 |
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77 | #define BSP_INT_DMA3 20 |
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78 | #define BSP_INT_SDI 21 |
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79 | #define BSP_INT_SPI0 22 |
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80 | #define BSP_INT_UART1 23 |
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81 | #define BSP_INT_USBD 25 |
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82 | #define BSP_INT_USBH 26 |
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83 | #define BSP_INT_IIC 27 |
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84 | #define BSP_INT_UART0 28 |
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85 | #define BSP_INT_SPI1 29 |
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86 | #define BSP_INT_RTC 30 |
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87 | #define BSP_INT_ADC 31 |
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88 | #define BSP_MAX_INT 32 |
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89 | #else |
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90 | #error "Undefined Samsung CPU model" |
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91 | #endif |
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92 | |
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93 | #define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) |
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94 | #define BSP_INTERRUPT_VECTOR_COUNT BSP_MAX_INT |
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95 | |
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96 | #endif /* _IRQ_H_ */ |
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97 | /* end of include file */ |
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