source: rtems/bsps/arm/smdk2410/include/bsp/irq.h @ cd5573c

Last change on this file since cd5573c was cd5573c, checked in by Sebastian Huber <sebastian.huber@…>, on 06/19/21 at 10:40:57

bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNT

Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT.

After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be
removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The
BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no
interrupt vector at all. Using COUNT instead of MAX may avoid some
interpretation issues, for example is the maximum value a valid vector number
or not.

Update #3269.

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/* irq.h
2 *
3 *  Copyright (c) 2010 embedded brains GmbH.
4 *
5 *  CopyRight (C) 2000 Canon Research France SA.
6 *  Emmanuel Raguet,  mailto:raguet@crf.canon.fr
7 *
8 *  Common file, merged from s3c2400/irq/irq.h and s3c2410/irq/irq.h
9 */
10
11#ifndef _IRQ_H_
12#define _IRQ_H_
13
14#include <rtems.h>
15#include <rtems/irq.h>
16#include <rtems/irq-extension.h>
17
18#include <s3c24xx.h>
19
20#ifdef CPU_S3C2400
21  /* possible interrupt sources */
22#define BSP_EINT0             0
23#define BSP_EINT1             1
24#define BSP_EINT2             2
25#define BSP_EINT3             3
26#define BSP_EINT4             4
27#define BSP_EINT5             5
28#define BSP_EINT6             6
29#define BSP_EINT7             7
30#define BSP_INT_TICK          8
31#define BSP_INT_WDT           9
32#define BSP_INT_TIMER0       10
33#define BSP_INT_TIMER1       11
34#define BSP_INT_TIMER2       12
35#define BSP_INT_TIMER3       13
36#define BSP_INT_TIMER4       14
37#define BSP_INT_UERR01       15
38#define _res0                16
39#define BSP_INT_DMA0         17
40#define BSP_INT_DMA1         18
41#define BSP_INT_DMA2         19
42#define BSP_INT_DMA3         20
43#define BSP_INT_MMC          21
44#define BSP_INT_SPI          22
45#define BSP_INT_URXD0        23
46#define BSP_INT_URXD1        24
47#define BSP_INT_USBD         25
48#define BSP_INT_USBH         26
49#define BSP_INT_IIC          27
50#define BSP_INT_UTXD0        28
51#define BSP_INT_UTXD1        29
52#define BSP_INT_RTC          30
53#define BSP_INT_ADC          31
54#define BSP_MAX_INT          32
55
56#elif defined CPU_S3C2410
57  /* possible interrupt sources */
58#define BSP_EINT0             0
59#define BSP_EINT1             1
60#define BSP_EINT2             2
61#define BSP_EINT3             3
62#define BSP_EINT4_7           4
63#define BSP_EINT8_23          5
64#define BSP_nBATT_FLT         7
65#define BSP_INT_TICK          8
66#define BSP_INT_WDT           9
67#define BSP_INT_TIMER0       10
68#define BSP_INT_TIMER1       11
69#define BSP_INT_TIMER2       12
70#define BSP_INT_TIMER3       13
71#define BSP_INT_TIMER4       14
72#define BSP_INT_UART2        15
73#define BSP_INT_LCD          16
74#define BSP_INT_DMA0         17
75#define BSP_INT_DMA1         18
76#define BSP_INT_DMA2         19
77#define BSP_INT_DMA3         20
78#define BSP_INT_SDI          21
79#define BSP_INT_SPI0         22
80#define BSP_INT_UART1        23
81#define BSP_INT_USBD         25
82#define BSP_INT_USBH         26
83#define BSP_INT_IIC          27
84#define BSP_INT_UART0        28
85#define BSP_INT_SPI1         29
86#define BSP_INT_RTC          30
87#define BSP_INT_ADC          31
88#define BSP_MAX_INT          32
89#else
90#error "Undefined Samsung CPU model"
91#endif
92
93#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1)
94#define BSP_INTERRUPT_VECTOR_COUNT BSP_MAX_INT
95
96#endif /* _IRQ_H_ */
97/* end of include file */
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