1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Boot and system start code. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2008, 2018 embedded brains GmbH. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Dornierstr. 4 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <rtems/asm.h> |
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22 | #include <rtems/score/percpu.h> |
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23 | |
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24 | #include <bspopts.h> |
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25 | #include <bsp/irq.h> |
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26 | |
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27 | /* Global symbols */ |
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28 | .globl _start |
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29 | .globl bsp_start_vector_table_begin |
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30 | .globl bsp_start_vector_table_end |
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31 | .globl bsp_start_vector_table_size |
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32 | .globl bsp_vector_table_size |
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33 | |
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34 | .section ".bsp_start_text", "ax" |
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35 | |
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36 | #if defined(ARM_MULTILIB_ARCH_V4) |
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37 | |
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38 | .globl bsp_start_hook_0_done |
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39 | |
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40 | #ifdef BSP_START_IN_HYP_SUPPORT |
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41 | .globl bsp_start_hyp_vector_table_begin |
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42 | #endif |
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43 | |
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44 | .arm |
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45 | |
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46 | /* |
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47 | * This is the exception vector table and the pointers to the default |
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48 | * exceptions handlers. |
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49 | */ |
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50 | |
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51 | bsp_start_vector_table_begin: |
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52 | |
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53 | ldr pc, handler_addr_reset |
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54 | ldr pc, handler_addr_undef |
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55 | ldr pc, handler_addr_swi |
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56 | ldr pc, handler_addr_prefetch |
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57 | ldr pc, handler_addr_abort |
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58 | |
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59 | /* Program signature checked by boot loader */ |
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60 | .word 0xb8a06f58 |
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61 | |
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62 | ldr pc, handler_addr_irq |
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63 | ldr pc, handler_addr_fiq |
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64 | |
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65 | handler_addr_reset: |
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66 | |
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67 | #ifdef BSP_START_RESET_VECTOR |
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68 | .word BSP_START_RESET_VECTOR |
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69 | #else |
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70 | .word _start |
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71 | #endif |
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72 | |
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73 | handler_addr_undef: |
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74 | |
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75 | .word _ARMV4_Exception_undef_default |
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76 | |
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77 | handler_addr_swi: |
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78 | |
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79 | .word _ARMV4_Exception_swi_default |
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80 | |
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81 | handler_addr_prefetch: |
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82 | |
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83 | .word _ARMV4_Exception_pref_abort_default |
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84 | |
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85 | handler_addr_abort: |
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86 | |
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87 | .word _ARMV4_Exception_data_abort_default |
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88 | |
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89 | handler_addr_reserved: |
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90 | |
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91 | .word _ARMV4_Exception_reserved_default |
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92 | |
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93 | handler_addr_irq: |
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94 | |
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95 | .word _ARMV4_Exception_interrupt |
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96 | |
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97 | handler_addr_fiq: |
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98 | |
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99 | .word _ARMV4_Exception_fiq_default |
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100 | |
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101 | bsp_start_vector_table_end: |
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102 | |
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103 | #ifdef BSP_START_IN_HYP_SUPPORT |
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104 | bsp_start_hyp_vector_table_begin: |
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105 | ldr pc, handler_addr_hyp_reset |
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106 | ldr pc, handler_addr_hyp_undef |
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107 | ldr pc, handler_addr_hyp_swi |
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108 | ldr pc, handler_addr_hyp_prefetch |
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109 | ldr pc, handler_addr_hyp_abort |
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110 | ldr pc, handler_addr_hyp_hyp |
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111 | ldr pc, handler_addr_hyp_irq |
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112 | ldr pc, handler_addr_hyp_fiq |
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113 | |
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114 | handler_addr_hyp_reset: |
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115 | .word _ARMV4_Exception_reserved_default |
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116 | |
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117 | handler_addr_hyp_undef: |
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118 | .word _ARMV4_Exception_reserved_default |
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119 | |
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120 | handler_addr_hyp_swi: |
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121 | .word _ARMV4_Exception_reserved_default |
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122 | |
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123 | handler_addr_hyp_prefetch: |
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124 | .word _ARMV4_Exception_reserved_default |
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125 | |
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126 | handler_addr_hyp_abort: |
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127 | .word _ARMV4_Exception_reserved_default |
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128 | |
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129 | handler_addr_hyp_hyp: |
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130 | .word _ARMV4_Exception_reserved_default |
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131 | |
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132 | handler_addr_hyp_irq: |
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133 | .word _ARMV4_Exception_reserved_default |
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134 | |
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135 | handler_addr_hyp_fiq: |
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136 | .word _ARMV4_Exception_reserved_default |
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137 | |
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138 | bsp_start_hyp_vector_table_end: |
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139 | #endif |
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140 | |
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141 | /* Start entry */ |
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142 | |
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143 | _start: |
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144 | |
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145 | /* |
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146 | * We do not save the context since we do not return to the boot |
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147 | * loader but preserve r1 and r2 to allow access to bootloader parameters |
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148 | */ |
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149 | #ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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150 | mov r5, r1 /* machine type number or ~0 for DT boot */ |
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151 | mov r6, r2 /* physical address of ATAGs or DTB */ |
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152 | #else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */ |
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153 | bl bsp_start_init_registers_core |
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154 | #endif |
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155 | |
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156 | #ifdef RTEMS_SMP |
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157 | /* Read MPIDR and get current processor index */ |
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158 | mrc p15, 0, r7, c0, c0, 5 |
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159 | and r7, #0xff |
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160 | #endif |
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161 | |
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162 | #ifdef BSP_START_COPY_FDT_FROM_U_BOOT |
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163 | #ifdef RTEMS_SMP |
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164 | cmp r7, #0 |
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165 | bne 1f |
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166 | #endif |
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167 | mov r0, r6 |
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168 | bl bsp_fdt_copy |
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169 | 1: |
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170 | #endif |
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171 | |
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172 | #ifdef RTEMS_SMP |
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173 | /* |
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174 | * Get current per-CPU control and store it in PL1 only Thread ID |
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175 | * Register (TPIDRPRW). |
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176 | */ |
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177 | ldr r1, =_Per_CPU_Information |
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178 | add r1, r1, r7, asl #PER_CPU_CONTROL_SIZE_LOG2 |
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179 | mcr p15, 0, r1, c13, c0, 4 |
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180 | |
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181 | #endif |
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182 | |
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183 | /* Calculate interrupt stack area end for current processor */ |
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184 | ldr r1, =_ISR_Stack_size |
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185 | #ifdef RTEMS_SMP |
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186 | add r7, #1 |
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187 | mul r1, r1, r7 |
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188 | #endif |
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189 | ldr r2, =_ISR_Stack_area_begin |
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190 | add r7, r1, r2 |
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191 | |
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192 | /* Save original CPSR value */ |
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193 | mrs r4, cpsr |
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194 | |
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195 | #ifdef BSP_START_IN_HYP_SUPPORT |
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196 | orr r0, r4, #(ARM_PSR_I | ARM_PSR_F) |
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197 | msr cpsr, r4 |
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198 | |
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199 | and r0, r4, #ARM_PSR_M_MASK |
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200 | cmp r0, #ARM_PSR_M_HYP |
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201 | bne bsp_start_skip_hyp_svc_switch |
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202 | |
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203 | /* Boot loader starts kernel in HYP mode, switch to SVC necessary */ |
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204 | ldr r1, =bsp_stack_hyp_size |
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205 | mov sp, r7 |
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206 | sub r7, r7, r1 |
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207 | bl bsp_start_arm_drop_hyp_mode |
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208 | |
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209 | bsp_start_skip_hyp_svc_switch: |
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210 | #endif |
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211 | /* Initialize stack pointer registers for the various modes */ |
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212 | |
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213 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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214 | mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) |
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215 | msr cpsr, r0 |
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216 | ldr r1, =bsp_stack_fiq_size |
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217 | mov sp, r7 |
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218 | sub r7, r7, r1 |
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219 | |
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220 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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221 | bl bsp_start_init_registers_banked_fiq |
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222 | #endif |
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223 | |
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224 | /* Enter ABT mode and set up the ABT stack pointer */ |
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225 | mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) |
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226 | msr cpsr, r0 |
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227 | ldr r1, =bsp_stack_abt_size |
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228 | mov sp, r7 |
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229 | sub r7, r7, r1 |
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230 | |
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231 | /* Enter UND mode and set up the UND stack pointer */ |
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232 | mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) |
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233 | msr cpsr, r0 |
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234 | ldr r1, =bsp_stack_und_size |
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235 | mov sp, r7 |
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236 | sub r7, r7, r1 |
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237 | |
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238 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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239 | mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) |
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240 | msr cpsr, r0 |
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241 | mov sp, r7 |
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242 | |
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243 | /* |
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244 | * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack |
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245 | * (interrupts are disabled). |
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246 | */ |
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247 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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248 | msr cpsr, r0 |
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249 | mov sp, r7 |
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250 | |
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251 | /* Stay in SVC mode */ |
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252 | |
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253 | #ifdef ARM_MULTILIB_VFP |
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254 | #ifdef ARM_MULTILIB_HAS_CPACR |
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255 | /* Read CPACR */ |
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256 | mrc p15, 0, r0, c1, c0, 2 |
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257 | |
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258 | /* Enable CP10 and CP11 */ |
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259 | orr r0, r0, #(1 << 20) |
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260 | orr r0, r0, #(1 << 22) |
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261 | |
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262 | /* |
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263 | * Clear ASEDIS and D32DIS. Writes to D32DIS are ignored for VFP-D16. |
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264 | */ |
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265 | bic r0, r0, #(3 << 30) |
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266 | |
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267 | /* Write CPACR */ |
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268 | mcr p15, 0, r0, c1, c0, 2 |
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269 | isb |
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270 | #endif |
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271 | |
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272 | /* Enable FPU */ |
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273 | mov r0, #(1 << 30) |
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274 | vmsr FPEXC, r0 |
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275 | |
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276 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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277 | bl bsp_start_init_registers_vfp |
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278 | #endif |
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279 | |
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280 | #endif /* ARM_MULTILIB_VFP */ |
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281 | |
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282 | /* |
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283 | * Branch to start hook 0. |
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284 | * |
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285 | * The previous code and parts of the start hook 0 may run with an |
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286 | * address offset. This implies that only branches relative to the |
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287 | * program counter are allowed. After the start hook 0 it is assumed |
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288 | * that the code can run at its intended position. Thus the link |
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289 | * register will be loaded with the absolute address. In THUMB mode |
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290 | * the start hook 0 must be within a 2kByte range due to the branch |
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291 | * instruction limitation. |
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292 | */ |
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293 | |
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294 | ldr lr, =bsp_start_hook_0_done |
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295 | #ifdef __thumb__ |
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296 | orr lr, #1 |
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297 | #endif |
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298 | |
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299 | SWITCH_FROM_ARM_TO_THUMB r0 |
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300 | |
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301 | mov r0, r4 /* original CPSR value */ |
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302 | mov r1, r5 /* machine type number or ~0 for DT boot */ |
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303 | mov r2, r6 /* physical address of ATAGs or DTB */ |
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304 | |
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305 | b bsp_start_hook_0 |
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306 | |
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307 | bsp_start_hook_0_done: |
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308 | |
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309 | SWITCH_FROM_THUMB_TO_ARM |
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310 | |
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311 | /* |
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312 | * Initialize the exception vectors. This includes the exceptions |
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313 | * vectors and the pointers to the default exception handlers. |
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314 | */ |
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315 | |
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316 | stmdb sp!, {r4, r5, r6} |
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317 | |
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318 | ldr r0, =bsp_vector_table_begin |
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319 | adr r1, bsp_start_vector_table_begin |
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320 | cmp r0, r1 |
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321 | beq bsp_vector_table_copy_done |
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322 | ldmia r1!, {r2-r9} |
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323 | stmia r0!, {r2-r9} |
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324 | ldmia r1!, {r2-r9} |
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325 | stmia r0!, {r2-r9} |
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326 | |
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327 | bsp_vector_table_copy_done: |
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328 | |
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329 | ldmia sp!, {r0, r1, r2} |
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330 | |
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331 | SWITCH_FROM_ARM_TO_THUMB r3 |
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332 | |
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333 | /* Branch to start hook 1 */ |
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334 | bl bsp_start_hook_1 |
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335 | |
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336 | /* Branch to boot card */ |
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337 | mov r0, #0 |
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338 | bl boot_card |
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339 | |
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340 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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341 | |
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342 | #include <rtems/score/armv7m.h> |
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343 | |
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344 | .syntax unified |
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345 | |
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346 | .thumb |
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347 | |
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348 | bsp_start_vector_table_begin: |
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349 | |
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350 | .word _ISR_Stack_area_end |
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351 | .word _start /* Reset */ |
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352 | .word _ARMV7M_Exception_default /* NMI */ |
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353 | .word _ARMV7M_Exception_default /* Hard Fault */ |
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354 | .word _ARMV7M_Exception_default /* MPU Fault */ |
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355 | .word _ARMV7M_Exception_default /* Bus Fault */ |
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356 | .word _ARMV7M_Exception_default /* Usage Fault */ |
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357 | .word _ARMV7M_Exception_default /* Reserved */ |
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358 | .word _ARMV7M_Exception_default /* Reserved */ |
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359 | .word _ARMV7M_Exception_default /* Reserved */ |
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360 | .word _ARMV7M_Exception_default /* Reserved */ |
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361 | .word _ARMV7M_Exception_default /* SVC */ |
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362 | .word _ARMV7M_Exception_default /* Debug Monitor */ |
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363 | .word _ARMV7M_Exception_default /* Reserved */ |
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364 | .word _ARMV7M_Exception_default /* PendSV */ |
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365 | .word _ARMV7M_Exception_default /* SysTick */ |
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366 | .rept BSP_INTERRUPT_VECTOR_MAX + 1 |
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367 | .word _ARMV7M_Exception_default /* IRQ */ |
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368 | .endr |
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369 | |
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370 | bsp_start_vector_table_end: |
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371 | |
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372 | .thumb_func |
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373 | |
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374 | _start: |
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375 | |
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376 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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377 | bl bsp_start_init_registers_core |
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378 | #endif |
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379 | |
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380 | #ifdef ARM_MULTILIB_VFP |
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381 | #ifdef ARM_MULTILIB_HAS_CPACR |
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382 | /* |
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383 | * Enable CP10 and CP11 coprocessors for privileged and user mode in |
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384 | * CPACR (bits 20-23). Ensure that write to register completes. |
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385 | */ |
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386 | ldr r0, =ARMV7M_CPACR |
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387 | ldr r1, [r0] |
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388 | orr r1, r1, #(0xf << 20) |
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389 | str r1, [r0] |
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390 | dsb |
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391 | isb |
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392 | #endif |
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393 | |
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394 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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395 | bl bsp_start_init_registers_vfp |
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396 | #endif |
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397 | |
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398 | #endif /* ARM_MULTILIB_VFP */ |
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399 | |
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400 | ldr sp, =_ISR_Stack_area_end |
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401 | ldr lr, =bsp_start_hook_0_done + 1 |
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402 | b bsp_start_hook_0 |
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403 | |
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404 | bsp_start_hook_0_done: |
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405 | |
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406 | bl bsp_start_hook_1 |
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407 | movs r0, #0 |
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408 | bl boot_card |
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409 | |
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410 | #endif /* defined(ARM_MULTILIB_ARCH_V7M) */ |
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411 | |
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412 | .set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin |
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413 | .set bsp_vector_table_size, bsp_start_vector_table_size |
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