source: rtems/bsps/arm/shared/irq/irq-gic.c @ e58ecb84

Last change on this file since e58ecb84 was e58ecb84, checked in by Sebastian Huber <sebastian.huber@…>, on Feb 21, 2020 at 1:21:33 PM

bsps/arm: Initialize priorities of PPIs

At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.

  • Property mode set to 100644
File size: 6.5 KB
Line 
1/*
2 * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bsp/arm-gic.h>
16
17#include <rtems/score/armv4.h>
18
19#include <libcpu/arm-cp15.h>
20
21#include <bsp/irq.h>
22#include <bsp/irq-generic.h>
23#include <bsp/start.h>
24
25#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
26
27#define PRIORITY_DEFAULT 127
28
29/*
30 * The following variants
31 *
32 *  - GICv1 with Security Extensions,
33 *  - GICv2 without Security Extensions, or
34 *  - within Secure processor mode
35 *
36 * have the ability to assign group 0 or 1 to individual interrupts.  Group
37 * 0 interrupts can be configured to raise an FIQ exception.  This enables
38 * the use of NMIs with respect to RTEMS.
39 *
40 * BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
41 * define.  Use arm_gic_irq_set_group() to change the group of an
42 * interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
43 * defined).
44 */
45#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
46#define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE)
47#define CPUIF_ICCICR \
48  (GIC_CPUIF_ICCICR_CBPR | GIC_CPUIF_ICCICR_FIQ_EN \
49    | GIC_CPUIF_ICCICR_ACK_CTL | GIC_CPUIF_ICCICR_ENABLE_GRP_1 \
50    | GIC_CPUIF_ICCICR_ENABLE)
51#else
52#define DIST_ICDDCR GIC_DIST_ICDDCR_ENABLE
53#define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE
54#endif
55
56void bsp_interrupt_dispatch(void)
57{
58  volatile gic_cpuif *cpuif = GIC_CPUIF;
59  uint32_t icciar = cpuif->icciar;
60  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
61  rtems_vector_number spurious = 1023;
62
63  if (vector != spurious) {
64    uint32_t psr = _ARMV4_Status_irq_enable();
65
66    bsp_interrupt_handler_dispatch(vector);
67
68    _ARMV4_Status_restore(psr);
69
70    cpuif->icceoir = icciar;
71  }
72}
73
74void bsp_interrupt_vector_enable(rtems_vector_number vector)
75{
76  volatile gic_dist *dist = ARM_GIC_DIST;
77
78  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
79
80  gic_id_enable(dist, vector);
81}
82
83void bsp_interrupt_vector_disable(rtems_vector_number vector)
84{
85  volatile gic_dist *dist = ARM_GIC_DIST;
86
87  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
88
89  gic_id_disable(dist, vector);
90}
91
92static inline uint32_t get_id_count(volatile gic_dist *dist)
93{
94  uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr);
95
96  id_count = 32 * (id_count + 1);
97  id_count = id_count <= 1020 ? id_count : 1020;
98
99  return id_count;
100}
101
102static void enable_fiq(void)
103{
104#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
105  rtems_interrupt_level level;
106
107  rtems_interrupt_local_disable(level);
108  level &= ~ARM_PSR_F;
109  rtems_interrupt_local_enable(level);
110#endif
111}
112
113rtems_status_code bsp_interrupt_facility_initialize(void)
114{
115  volatile gic_cpuif *cpuif = GIC_CPUIF;
116  volatile gic_dist *dist = ARM_GIC_DIST;
117  uint32_t id_count = get_id_count(dist);
118  uint32_t id;
119
120  arm_cp15_set_exception_handler(
121    ARM_EXCEPTION_IRQ,
122    _ARMV4_Exception_interrupt
123  );
124
125  for (id = 0; id < id_count; id += 32) {
126#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
127    dist->icdigr[id / 32] = 0xffffffff;
128#endif
129    dist->icdicer[id / 32] = 0xffffffff;
130  }
131
132  for (id = 0; id < id_count; ++id) {
133    gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
134  }
135
136  for (id = 32; id < id_count; ++id) {
137    gic_id_set_targets(dist, id, 0x01);
138  }
139
140  cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
141  cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
142  cpuif->iccicr = CPUIF_ICCICR;
143
144  dist->icddcr = GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE;
145
146  enable_fiq();
147  return RTEMS_SUCCESSFUL;
148}
149
150#ifdef RTEMS_SMP
151BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
152{
153  volatile gic_cpuif *cpuif = GIC_CPUIF;
154  volatile gic_dist *dist = ARM_GIC_DIST;
155  uint32_t id;
156
157  while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
158    /* Wait */
159  }
160
161#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
162  dist->icdigr[0] = 0xffffffff;
163#endif
164
165  /* Initialize Peripheral Private Interrupts (PPIs) */
166  for (id = 0; id < 32; ++id) {
167    gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
168  }
169
170  cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
171  cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
172  cpuif->iccicr = CPUIF_ICCICR;
173
174  enable_fiq();
175}
176#endif
177
178rtems_status_code arm_gic_irq_set_priority(
179  rtems_vector_number vector,
180  uint8_t priority
181)
182{
183  rtems_status_code sc = RTEMS_SUCCESSFUL;
184
185  if (bsp_interrupt_is_valid_vector(vector)) {
186    volatile gic_dist *dist = ARM_GIC_DIST;
187
188    gic_id_set_priority(dist, vector, priority);
189  } else {
190    sc = RTEMS_INVALID_ID;
191  }
192
193  return sc;
194}
195
196rtems_status_code arm_gic_irq_get_priority(
197  rtems_vector_number vector,
198  uint8_t *priority
199)
200{
201  rtems_status_code sc = RTEMS_SUCCESSFUL;
202
203  if (bsp_interrupt_is_valid_vector(vector)) {
204    volatile gic_dist *dist = ARM_GIC_DIST;
205
206    *priority = gic_id_get_priority(dist, vector);
207  } else {
208    sc = RTEMS_INVALID_ID;
209  }
210
211  return sc;
212}
213
214rtems_status_code arm_gic_irq_set_group(
215  rtems_vector_number vector,
216  gic_group group
217)
218{
219  rtems_status_code sc = RTEMS_SUCCESSFUL;
220
221  if (bsp_interrupt_is_valid_vector(vector)) {
222    volatile gic_dist *dist = ARM_GIC_DIST;
223
224    gic_id_set_group(dist, vector, group);
225  } else {
226    sc = RTEMS_INVALID_ID;
227  }
228
229  return sc;
230}
231
232rtems_status_code arm_gic_irq_get_group(
233  rtems_vector_number vector,
234  gic_group *group
235)
236{
237  rtems_status_code sc = RTEMS_SUCCESSFUL;
238
239  if (bsp_interrupt_is_valid_vector(vector)) {
240    volatile gic_dist *dist = ARM_GIC_DIST;
241
242    *group = gic_id_get_group(dist, vector);
243  } else {
244    sc = RTEMS_INVALID_ID;
245  }
246
247  return sc;
248}
249
250void bsp_interrupt_set_affinity(
251  rtems_vector_number vector,
252  const Processor_mask *affinity
253)
254{
255  volatile gic_dist *dist = ARM_GIC_DIST;
256  uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
257
258  gic_id_set_targets(dist, vector, targets);
259}
260
261void bsp_interrupt_get_affinity(
262  rtems_vector_number vector,
263  Processor_mask *affinity
264)
265{
266  volatile gic_dist *dist = ARM_GIC_DIST;
267  uint8_t targets = gic_id_get_targets(dist, vector);
268
269  _Processor_mask_From_uint32_t(affinity, targets, 0);
270}
271
272void arm_gic_trigger_sgi(
273  rtems_vector_number vector,
274  arm_gic_irq_software_irq_target_filter filter,
275  uint8_t targets
276)
277{
278  volatile gic_dist *dist = ARM_GIC_DIST;
279
280  dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
281    | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
282#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
283    | GIC_DIST_ICDSGIR_NSATT
284#endif
285    | GIC_DIST_ICDSGIR_SGIINTID(vector);
286}
Note: See TracBrowser for help on using the repository browser.