1 | /* |
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2 | * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp/arm-gic.h> |
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16 | |
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17 | #include <rtems/score/armv4.h> |
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18 | |
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19 | #include <libcpu/arm-cp15.h> |
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20 | |
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21 | #include <bsp/irq.h> |
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22 | #include <bsp/irq-generic.h> |
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23 | #include <bsp/start.h> |
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24 | |
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25 | #define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE) |
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26 | |
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27 | #define PRIORITY_DEFAULT 127 |
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28 | |
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29 | /* |
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30 | * The following variants |
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31 | * |
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32 | * - GICv1 with Security Extensions, |
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33 | * - GICv2 without Security Extensions, or |
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34 | * - within Secure processor mode |
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35 | * |
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36 | * have the ability to assign group 0 or 1 to individual interrupts. Group |
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37 | * 0 interrupts can be configured to raise an FIQ exception. This enables |
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38 | * the use of NMIs with respect to RTEMS. |
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39 | * |
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40 | * BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
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41 | * define. Use arm_gic_irq_set_group() to change the group of an |
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42 | * interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is |
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43 | * defined). |
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44 | */ |
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45 | #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
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46 | #define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE) |
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47 | #define CPUIF_ICCICR \ |
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48 | (GIC_CPUIF_ICCICR_CBPR | GIC_CPUIF_ICCICR_FIQ_EN \ |
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49 | | GIC_CPUIF_ICCICR_ACK_CTL | GIC_CPUIF_ICCICR_ENABLE_GRP_1 \ |
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50 | | GIC_CPUIF_ICCICR_ENABLE) |
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51 | #else |
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52 | #define DIST_ICDDCR GIC_DIST_ICDDCR_ENABLE |
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53 | #define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE |
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54 | #endif |
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55 | |
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56 | void bsp_interrupt_dispatch(void) |
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57 | { |
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58 | volatile gic_cpuif *cpuif = GIC_CPUIF; |
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59 | uint32_t icciar = cpuif->icciar; |
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60 | rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); |
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61 | rtems_vector_number spurious = 1023; |
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62 | |
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63 | if (vector != spurious) { |
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64 | uint32_t psr = _ARMV4_Status_irq_enable(); |
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65 | |
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66 | bsp_interrupt_handler_dispatch(vector); |
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67 | |
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68 | _ARMV4_Status_restore(psr); |
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69 | |
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70 | cpuif->icceoir = icciar; |
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71 | } |
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72 | } |
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73 | |
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74 | void bsp_interrupt_vector_enable(rtems_vector_number vector) |
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75 | { |
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76 | volatile gic_dist *dist = ARM_GIC_DIST; |
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77 | |
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78 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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79 | |
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80 | gic_id_enable(dist, vector); |
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81 | } |
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82 | |
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83 | void bsp_interrupt_vector_disable(rtems_vector_number vector) |
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84 | { |
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85 | volatile gic_dist *dist = ARM_GIC_DIST; |
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86 | |
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87 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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88 | |
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89 | gic_id_disable(dist, vector); |
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90 | } |
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91 | |
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92 | static inline uint32_t get_id_count(volatile gic_dist *dist) |
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93 | { |
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94 | uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr); |
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95 | |
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96 | id_count = 32 * (id_count + 1); |
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97 | id_count = id_count <= 1020 ? id_count : 1020; |
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98 | |
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99 | return id_count; |
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100 | } |
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101 | |
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102 | static void enable_fiq(void) |
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103 | { |
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104 | #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
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105 | rtems_interrupt_level level; |
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106 | |
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107 | rtems_interrupt_local_disable(level); |
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108 | level &= ~ARM_PSR_F; |
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109 | rtems_interrupt_local_enable(level); |
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110 | #endif |
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111 | } |
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112 | |
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113 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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114 | { |
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115 | volatile gic_cpuif *cpuif = GIC_CPUIF; |
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116 | volatile gic_dist *dist = ARM_GIC_DIST; |
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117 | uint32_t id_count = get_id_count(dist); |
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118 | uint32_t id; |
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119 | |
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120 | arm_cp15_set_exception_handler( |
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121 | ARM_EXCEPTION_IRQ, |
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122 | _ARMV4_Exception_interrupt |
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123 | ); |
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124 | |
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125 | for (id = 0; id < id_count; id += 32) { |
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126 | #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
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127 | dist->icdigr[id / 32] = 0xffffffff; |
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128 | #endif |
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129 | dist->icdicer[id / 32] = 0xffffffff; |
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130 | } |
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131 | |
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132 | for (id = 0; id < id_count; ++id) { |
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133 | gic_id_set_priority(dist, id, PRIORITY_DEFAULT); |
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134 | } |
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135 | |
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136 | for (id = 32; id < id_count; ++id) { |
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137 | gic_id_set_targets(dist, id, 0x01); |
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138 | } |
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139 | |
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140 | cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); |
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141 | cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); |
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142 | cpuif->iccicr = CPUIF_ICCICR; |
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143 | |
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144 | dist->icddcr = GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE; |
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145 | |
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146 | enable_fiq(); |
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147 | return RTEMS_SUCCESSFUL; |
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148 | } |
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149 | |
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150 | #ifdef RTEMS_SMP |
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151 | BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) |
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152 | { |
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153 | volatile gic_cpuif *cpuif = GIC_CPUIF; |
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154 | volatile gic_dist *dist = ARM_GIC_DIST; |
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155 | uint32_t id; |
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156 | |
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157 | while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { |
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158 | /* Wait */ |
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159 | } |
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160 | |
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161 | #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
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162 | dist->icdigr[0] = 0xffffffff; |
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163 | #endif |
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164 | |
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165 | /* Initialize Peripheral Private Interrupts (PPIs) */ |
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166 | for (id = 0; id < 32; ++id) { |
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167 | gic_id_set_priority(dist, id, PRIORITY_DEFAULT); |
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168 | } |
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169 | |
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170 | cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); |
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171 | cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); |
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172 | cpuif->iccicr = CPUIF_ICCICR; |
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173 | |
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174 | enable_fiq(); |
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175 | } |
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176 | #endif |
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177 | |
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178 | rtems_status_code arm_gic_irq_set_priority( |
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179 | rtems_vector_number vector, |
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180 | uint8_t priority |
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181 | ) |
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182 | { |
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183 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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184 | |
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185 | if (bsp_interrupt_is_valid_vector(vector)) { |
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186 | volatile gic_dist *dist = ARM_GIC_DIST; |
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187 | |
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188 | gic_id_set_priority(dist, vector, priority); |
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189 | } else { |
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190 | sc = RTEMS_INVALID_ID; |
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191 | } |
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192 | |
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193 | return sc; |
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194 | } |
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195 | |
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196 | rtems_status_code arm_gic_irq_get_priority( |
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197 | rtems_vector_number vector, |
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198 | uint8_t *priority |
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199 | ) |
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200 | { |
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201 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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202 | |
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203 | if (bsp_interrupt_is_valid_vector(vector)) { |
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204 | volatile gic_dist *dist = ARM_GIC_DIST; |
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205 | |
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206 | *priority = gic_id_get_priority(dist, vector); |
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207 | } else { |
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208 | sc = RTEMS_INVALID_ID; |
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209 | } |
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210 | |
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211 | return sc; |
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212 | } |
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213 | |
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214 | rtems_status_code arm_gic_irq_set_group( |
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215 | rtems_vector_number vector, |
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216 | gic_group group |
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217 | ) |
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218 | { |
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219 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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220 | |
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221 | if (bsp_interrupt_is_valid_vector(vector)) { |
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222 | volatile gic_dist *dist = ARM_GIC_DIST; |
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223 | |
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224 | gic_id_set_group(dist, vector, group); |
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225 | } else { |
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226 | sc = RTEMS_INVALID_ID; |
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227 | } |
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228 | |
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229 | return sc; |
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230 | } |
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231 | |
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232 | rtems_status_code arm_gic_irq_get_group( |
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233 | rtems_vector_number vector, |
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234 | gic_group *group |
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235 | ) |
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236 | { |
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237 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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238 | |
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239 | if (bsp_interrupt_is_valid_vector(vector)) { |
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240 | volatile gic_dist *dist = ARM_GIC_DIST; |
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241 | |
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242 | *group = gic_id_get_group(dist, vector); |
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243 | } else { |
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244 | sc = RTEMS_INVALID_ID; |
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245 | } |
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246 | |
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247 | return sc; |
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248 | } |
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249 | |
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250 | void bsp_interrupt_set_affinity( |
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251 | rtems_vector_number vector, |
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252 | const Processor_mask *affinity |
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253 | ) |
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254 | { |
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255 | volatile gic_dist *dist = ARM_GIC_DIST; |
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256 | uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0); |
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257 | |
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258 | gic_id_set_targets(dist, vector, targets); |
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259 | } |
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260 | |
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261 | void bsp_interrupt_get_affinity( |
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262 | rtems_vector_number vector, |
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263 | Processor_mask *affinity |
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264 | ) |
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265 | { |
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266 | volatile gic_dist *dist = ARM_GIC_DIST; |
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267 | uint8_t targets = gic_id_get_targets(dist, vector); |
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268 | |
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269 | _Processor_mask_From_uint32_t(affinity, targets, 0); |
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270 | } |
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271 | |
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272 | void arm_gic_trigger_sgi( |
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273 | rtems_vector_number vector, |
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274 | arm_gic_irq_software_irq_target_filter filter, |
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275 | uint8_t targets |
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276 | ) |
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277 | { |
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278 | volatile gic_dist *dist = ARM_GIC_DIST; |
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279 | |
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280 | dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) |
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281 | | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) |
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282 | #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 |
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283 | | GIC_DIST_ICDSGIR_NSATT |
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284 | #endif |
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285 | | GIC_DIST_ICDSGIR_SGIINTID(vector); |
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286 | } |
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