1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* |
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4 | * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) |
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5 | * Copyright (C) 2011, 2012 Sebastian Huber |
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6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * 1. Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * 2. Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * |
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16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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26 | * POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | #include <bsp/irq-generic.h> |
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30 | #include <bsp.h> |
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31 | #include <bsp/irq.h> |
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32 | #include <bsp/linker-symbols.h> |
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33 | #include <bsp/armv7m-irq.h> |
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34 | |
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35 | #include <rtems/score/armv7m.h> |
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36 | |
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37 | #include <string.h> |
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38 | |
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39 | #ifdef ARM_MULTILIB_ARCH_V7M |
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40 | |
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41 | rtems_status_code bsp_interrupt_get_attributes( |
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42 | rtems_vector_number vector, |
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43 | rtems_interrupt_attributes *attributes |
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44 | ) |
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45 | { |
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46 | return RTEMS_SUCCESSFUL; |
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47 | } |
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48 | |
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49 | rtems_status_code bsp_interrupt_is_pending( |
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50 | rtems_vector_number vector, |
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51 | bool *pending |
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52 | ) |
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53 | { |
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54 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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55 | bsp_interrupt_assert(pending != NULL); |
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56 | *pending = false; |
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57 | return RTEMS_UNSATISFIED; |
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58 | } |
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59 | |
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60 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
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61 | { |
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62 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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63 | return RTEMS_UNSATISFIED; |
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64 | } |
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65 | |
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66 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
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67 | { |
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68 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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69 | return RTEMS_UNSATISFIED; |
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70 | } |
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71 | |
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72 | rtems_status_code bsp_interrupt_vector_is_enabled( |
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73 | rtems_vector_number vector, |
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74 | bool *enabled |
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75 | ) |
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76 | { |
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77 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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78 | bsp_interrupt_assert(enabled != NULL); |
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79 | *enabled = false; |
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80 | return RTEMS_UNSATISFIED; |
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81 | } |
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82 | |
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83 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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84 | { |
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85 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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86 | _ARMV7M_NVIC_Set_enable((int) vector); |
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87 | return RTEMS_SUCCESSFUL; |
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88 | } |
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89 | |
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90 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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91 | { |
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92 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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93 | _ARMV7M_NVIC_Clear_enable((int) vector); |
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94 | return RTEMS_SUCCESSFUL; |
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95 | } |
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96 | |
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97 | void bsp_interrupt_facility_initialize(void) |
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98 | { |
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99 | ARMV7M_Exception_handler *vector_table; |
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100 | int i; |
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101 | |
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102 | vector_table = (ARMV7M_Exception_handler *) bsp_vector_table_begin; |
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103 | |
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104 | if (bsp_vector_table_begin != bsp_start_vector_table_begin) { |
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105 | memcpy( |
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106 | vector_table, |
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107 | bsp_start_vector_table_begin, |
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108 | (size_t) bsp_vector_table_size |
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109 | ); |
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110 | } |
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111 | |
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112 | _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR | ARMV7M_SCB_ICSR_PENDSTCLR; |
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113 | |
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114 | for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) { |
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115 | _ARMV7M_NVIC_Clear_enable(i); |
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116 | _ARMV7M_NVIC_Clear_pending(i); |
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117 | _ARMV7M_NVIC_Set_priority(i, BSP_ARMV7M_IRQ_PRIORITY_DEFAULT); |
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118 | } |
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119 | |
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120 | _ARMV7M_SCB->vtor = vector_table; |
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121 | } |
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122 | |
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123 | #endif /* ARM_MULTILIB_ARCH_V7M */ |
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