1 | /* |
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2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | #include <libcpu/arm-cp15.h> |
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10 | |
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11 | #include <bsp/linker-symbols.h> |
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12 | |
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13 | void* arm_cp15_set_exception_handler( |
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14 | Arm_symbolic_exception_name exception, |
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15 | void (*handler)(void) |
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16 | ) |
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17 | { |
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18 | uint32_t current_handler = 0; |
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19 | |
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20 | if ((unsigned) exception < MAX_EXCEPTIONS) { |
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21 | uint32_t *cpu_table = (uint32_t *) 0 + MAX_EXCEPTIONS; |
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22 | uint32_t *mirror_table = (uint32_t *) bsp_vector_table_begin + MAX_EXCEPTIONS; |
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23 | |
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24 | current_handler = mirror_table[exception]; |
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25 | |
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26 | if (current_handler != (uint32_t) handler) { |
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27 | size_t table_size = MAX_EXCEPTIONS * sizeof(uint32_t); |
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28 | uint32_t cls = arm_cp15_get_min_cache_line_size(); |
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29 | uint32_t ctrl; |
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30 | rtems_interrupt_level level; |
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31 | |
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32 | rtems_interrupt_local_disable(level); |
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33 | |
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34 | ctrl = arm_cp15_mmu_disable(cls); |
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35 | |
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36 | mirror_table[exception] = (uint32_t) handler; |
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37 | |
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38 | rtems_cache_flush_multiple_data_lines(mirror_table, table_size); |
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39 | |
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40 | /* |
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41 | * On ARMv7 processors with the Security Extension the mirror table might |
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42 | * be the actual table used by the processor. |
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43 | */ |
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44 | rtems_cache_invalidate_multiple_instruction_lines(mirror_table, table_size); |
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45 | |
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46 | rtems_cache_invalidate_multiple_instruction_lines(cpu_table, table_size); |
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47 | |
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48 | arm_cp15_set_control(ctrl); |
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49 | |
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50 | rtems_interrupt_local_enable(level); |
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51 | } |
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52 | } |
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53 | |
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54 | return (void*) current_handler; |
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55 | } |
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