1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <rtems.h> |
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16 | #include <chip.h> |
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17 | |
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18 | #define CPU_DATA_CACHE_ALIGNMENT 32 |
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19 | |
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20 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 |
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21 | |
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22 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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23 | |
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24 | static inline void _CPU_cache_flush_data_range( |
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25 | const void *d_addr, |
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26 | size_t n_bytes |
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27 | ) |
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28 | { |
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29 | SCB_CleanInvalidateDCache_by_Addr( |
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30 | RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr), |
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31 | n_bytes |
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32 | ); |
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33 | } |
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34 | |
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35 | static inline void _CPU_cache_invalidate_data_range( |
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36 | const void *d_addr, |
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37 | size_t n_bytes |
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38 | ) |
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39 | { |
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40 | SCB_InvalidateDCache_by_Addr( |
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41 | RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr), |
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42 | n_bytes |
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43 | ); |
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44 | } |
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45 | |
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46 | static inline void _CPU_cache_freeze_data(void) |
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47 | { |
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48 | /* TODO */ |
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49 | } |
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50 | |
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51 | static inline void _CPU_cache_unfreeze_data(void) |
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52 | { |
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53 | /* TODO */ |
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54 | } |
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55 | |
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56 | static inline void _CPU_cache_invalidate_instruction_range( |
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57 | const void *i_addr, |
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58 | size_t n_bytes |
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59 | ) |
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60 | { |
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61 | rtems_interrupt_level level; |
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62 | |
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63 | rtems_interrupt_disable(level); |
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64 | SCB_InvalidateICache(); |
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65 | rtems_interrupt_enable(level); |
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66 | } |
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67 | |
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68 | static inline void _CPU_cache_freeze_instruction(void) |
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69 | { |
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70 | /* TODO */ |
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71 | } |
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72 | |
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73 | static inline void _CPU_cache_unfreeze_instruction(void) |
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74 | { |
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75 | /* TODO */ |
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76 | } |
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77 | |
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78 | static inline void _CPU_cache_flush_entire_data(void) |
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79 | { |
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80 | rtems_interrupt_level level; |
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81 | |
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82 | rtems_interrupt_disable(level); |
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83 | SCB_CleanDCache(); |
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84 | rtems_interrupt_enable(level); |
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85 | } |
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86 | |
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87 | static inline void _CPU_cache_invalidate_entire_data(void) |
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88 | { |
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89 | rtems_interrupt_level level; |
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90 | |
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91 | rtems_interrupt_disable(level); |
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92 | SCB_InvalidateDCache(); |
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93 | rtems_interrupt_enable(level); |
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94 | } |
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95 | |
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96 | static inline void _CPU_cache_enable_data(void) |
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97 | { |
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98 | rtems_interrupt_level level; |
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99 | |
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100 | rtems_interrupt_disable(level); |
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101 | SCB_EnableDCache(); |
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102 | rtems_interrupt_enable(level); |
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103 | } |
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104 | |
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105 | static inline void _CPU_cache_disable_data(void) |
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106 | { |
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107 | rtems_interrupt_level level; |
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108 | |
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109 | rtems_interrupt_disable(level); |
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110 | SCB_DisableDCache(); |
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111 | rtems_interrupt_enable(level); |
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112 | } |
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113 | |
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114 | static inline void _CPU_cache_invalidate_entire_instruction(void) |
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115 | { |
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116 | rtems_interrupt_level level; |
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117 | |
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118 | rtems_interrupt_disable(level); |
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119 | SCB_InvalidateICache(); |
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120 | rtems_interrupt_enable(level); |
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121 | } |
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122 | |
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123 | static inline void _CPU_cache_enable_instruction(void) |
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124 | { |
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125 | rtems_interrupt_level level; |
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126 | |
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127 | rtems_interrupt_disable(level); |
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128 | SCB_EnableICache(); |
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129 | rtems_interrupt_enable(level); |
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130 | } |
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131 | |
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132 | static inline void _CPU_cache_disable_instruction(void) |
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133 | { |
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134 | rtems_interrupt_level level; |
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135 | |
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136 | rtems_interrupt_disable(level); |
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137 | SCB_DisableICache(); |
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138 | rtems_interrupt_enable(level); |
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139 | } |
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140 | |
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141 | #include "../../shared/cache/cacheimpl.h" |
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