source: rtems/bsps/arm/shared/cache/cache-v7ar-disable-data.S @ e7d623e7

Last change on this file since e7d623e7 was e7d623e7, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 10, 2019 at 6:57:36 AM

bsps/arm: Conditional ARMv7-AR data cache disable

Update #3667.
Close #3674.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2018 embedded brains GmbH
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <rtems/asm.h>
29
30#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 65 || __ARM_ARCH_PROFILE == 82)
31        .globl  rtems_cache_disable_data
32
33        .syntax unified
34        .section        .text
35        .arm
36
37        /*
38         * This function disables the data cache on an ARMv7-AR compatible
39         * processor.
40         */
41FUNCTION_ENTRY(rtems_cache_disable_data)
42        /* Disable interrupts */
43        mrs     r0, CPSR
44        orr     r1, r0, #0x80
45        msr     CPSR_fc, r1
46
47        stmdb   sp!, {r4 - r11, lr}
48        dmb
49
50        /* Disable data cache in SCTLR */
51        mrc     p15, 0, r1, c1, c0, 0
52        bic     r1, r1, #0x4
53        mcr     p15, 0, r1, c1, c0, 0
54        isb
55
56        /* Get cache levels (LoC) from CLIDR */
57        mrc     p15, 1, r1, c0, c0, 1
58        mov     r2, r1, lsr #24
59        ands    r2, r2, #0x7
60        beq     .Ldone
61
62        /* Start with level 0 */
63        mov     r3, #0
64
65.Lflush_level:
66        /* Flush level specified by r3 */
67
68        /* Check cache type */
69        add     r4, r3, r3, lsl #1
70        lsr     r5, r1, r4
71        and     r5, r5, #0x7
72        cmp     r5, #2
73        blt     .Lno_data_cache
74
75        /* Read CCSIDR */
76        lsl     r4, r3, #1
77        mcr     p15, 2, r4, c0, c0, 0
78        isb
79        mrc     p15, 1, r5, c0, c0, 0
80
81        /* Get cache line power */
82        and     r6, r5, #0x7
83        add     r6, r6, #4
84
85        /* Get ways minus one */
86        mov     r7, #0x3ff
87        ands    r7, r7, r5, lsr #3
88
89        /* Get way shift */
90        clz     r8, r7
91
92        /* Get sets minus one */
93        mov     r9, #0x7fff
94        ands    r9, r9, r5, lsr #13
95
96.Lloop_over_ways:
97        mov     r10, r9
98
99.Lloop_over_sets:
100        orr     r11, r4, r7, lsl r8
101        orr     r11, r11, r10, lsl r6
102
103        /* Clean and invalidate by set and way */
104        mcr     p15, 0, r11, c7, c14, 2
105
106        subs    r10, r10, #1
107        bge     .Lloop_over_sets
108        subs    r7, r7, #1
109        bge     .Lloop_over_ways
110
111.Lno_data_cache:
112        /* Next level */
113        add     r3, r3, #1
114        cmp     r2, r3
115        bgt     .Lflush_level
116
117.Ldone:
118        /* Restore interrupts */
119        msr     CPSR_fc, r0
120
121        ldmia   sp!, {r4 - r11, pc}
122#endif
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