source: rtems/bsps/arm/shared/cache/cache-v7ar-disable-data.S @ 0abe47f

Last change on this file since 0abe47f was 0abe47f, checked in by Thomas Dörfler <thomas.doerfler@…>, on Jan 10, 2019 at 6:29:54 AM

bsps/arm: Fix typo in disable cache for ARMv7-AR

Update #3667.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2018 embedded brains GmbH
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <rtems/asm.h>
29
30        .globl  rtems_cache_disable_data
31
32        .syntax unified
33        .section        .text
34        .arm
35
36        /*
37         * This function disables the data cache on an ARMv7-AR compatible
38         * processor.
39         */
40FUNCTION_ENTRY(rtems_cache_disable_data)
41        /* Disable interrupts */
42        mrs     r0, CPSR
43        orr     r1, r0, #0x80
44        msr     CPSR_fc, r1
45
46        stmdb   sp!, {r4 - r11, lr}
47        dmb
48
49        /* Disable data cache in SCTLR */
50        mrc     p15, 0, r1, c1, c0, 0
51        bic     r1, r1, #0x4
52        mcr     p15, 0, r1, c1, c0, 0
53        isb
54
55        /* Get cache levels (LoC) from CLIDR */
56        mrc     p15, 1, r1, c0, c0, 1
57        mov     r2, r1, lsr #24
58        ands    r2, r2, #0x7
59        beq     .Ldone
60
61        /* Start with level 0 */
62        mov     r3, #0
63
64.Lflush_level:
65        /* Flush level specified by r3 */
66
67        /* Check cache type */
68        add     r4, r3, r3, lsl #1
69        lsr     r5, r1, r4
70        and     r5, r5, #0x7
71        cmp     r5, #2
72        blt     .Lno_data_cache
73
74        /* Read CCSIDR */
75        lsl     r4, r3, #1
76        mcr     p15, 2, r4, c0, c0, 0
77        isb
78        mrc     p15, 1, r5, c0, c0, 0
79
80        /* Get cache line power */
81        and     r6, r5, #0x7
82        add     r6, r6, #4
83
84        /* Get ways minus one */
85        mov     r7, #0x3ff
86        ands    r7, r7, r5, lsr #3
87
88        /* Get way shift */
89        clz     r8, r7
90
91        /* Get sets minus one */
92        mov     r9, #0x7fff
93        ands    r9, r9, r5, lsr #13
94
95.Lloop_over_ways:
96        mov     r10, r9
97
98.Lloop_over_sets:
99        orr     r11, r4, r7, lsl r8
100        orr     r11, r11, r10, lsl r6
101
102        /* Clean and invalidate by set and way */
103        mcr     p15, 0, r11, c7, c14, 2
104
105        subs    r10, r10, #1
106        bge     .Lloop_over_sets
107        subs    r7, r7, #1
108        bge     .Lloop_over_ways
109
110.Lno_data_cache:
111        /* Next level */
112        add     r3, r3, #1
113        cmp     r2, r3
114        bgt     .Lflush_level
115
116.Ldone:
117        /* Restore interrupts */
118        msr     CPSR_fc, r0
119
120        ldmia   sp!, {r4 - r11, pc}
Note: See TracBrowser for help on using the repository browser.