1 | /** |
---|
2 | * @ingroup L2C-310_cache |
---|
3 | * |
---|
4 | * @brief Cache definitions and functions. |
---|
5 | * |
---|
6 | * This file implements handling for the ARM L2C-310 cache controller |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * Authorship |
---|
11 | * ---------- |
---|
12 | * This software was created by |
---|
13 | * R. Claus <claus@slac.stanford.edu>, 2013, |
---|
14 | * Stanford Linear Accelerator Center, Stanford University. |
---|
15 | * |
---|
16 | * Acknowledgement of sponsorship |
---|
17 | * ------------------------------ |
---|
18 | * This software was produced by |
---|
19 | * the Stanford Linear Accelerator Center, Stanford University, |
---|
20 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
---|
21 | * |
---|
22 | * Government disclaimer of liability |
---|
23 | * ---------------------------------- |
---|
24 | * Neither the United States nor the United States Department of Energy, |
---|
25 | * nor any of their employees, makes any warranty, express or implied, or |
---|
26 | * assumes any legal liability or responsibility for the accuracy, |
---|
27 | * completeness, or usefulness of any data, apparatus, product, or process |
---|
28 | * disclosed, or represents that its use would not infringe privately owned |
---|
29 | * rights. |
---|
30 | * |
---|
31 | * Stanford disclaimer of liability |
---|
32 | * -------------------------------- |
---|
33 | * Stanford University makes no representations or warranties, express or |
---|
34 | * implied, nor assumes any liability for the use of this software. |
---|
35 | * |
---|
36 | * Stanford disclaimer of copyright |
---|
37 | * -------------------------------- |
---|
38 | * Stanford University, owner of the copyright, hereby disclaims its |
---|
39 | * copyright and all other rights in this software. Hence, anyone may |
---|
40 | * freely use it for any purpose without restriction. |
---|
41 | * |
---|
42 | * Maintenance of notices |
---|
43 | * ---------------------- |
---|
44 | * In the interest of clarity regarding the origin and status of this |
---|
45 | * SLAC software, this and all the preceding Stanford University notices |
---|
46 | * are to remain affixed to any copy or derivative of this software made |
---|
47 | * or distributed by the recipient and are to be affixed to any copy of |
---|
48 | * software made or distributed by the recipient that contains a copy or |
---|
49 | * derivative of this software. |
---|
50 | * |
---|
51 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
---|
52 | */ |
---|
53 | |
---|
54 | #include <assert.h> |
---|
55 | #include <bsp.h> |
---|
56 | #include <bsp/fatal.h> |
---|
57 | #include <libcpu/arm-cp15.h> |
---|
58 | #include <rtems/rtems/intr.h> |
---|
59 | #include <bsp/arm-release-id.h> |
---|
60 | #include <bsp/arm-errata.h> |
---|
61 | |
---|
62 | #include "cache-cp15.h" |
---|
63 | |
---|
64 | /* These two defines also ensure that the rtems_cache_* functions have bodies */ |
---|
65 | #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT |
---|
66 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT |
---|
67 | #if defined(__ARM_ARCH_7A__) |
---|
68 | /* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */ |
---|
69 | #define CPU_MAXIMAL_CACHE_ALIGNMENT 64 |
---|
70 | #endif |
---|
71 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ |
---|
72 | ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
---|
73 | #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |
---|
74 | |
---|
75 | #define L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 ) |
---|
76 | #define L2C_310_INSTRUCTION_LINE_MASK \ |
---|
77 | ( CPU_INSTRUCTION_CACHE_ALIGNMENT \ |
---|
78 | - 1 ) |
---|
79 | #define L2C_310_NUM_WAYS 8 |
---|
80 | #define L2C_310_WAY_MASK ( ( 1 << L2C_310_NUM_WAYS ) - 1 ) |
---|
81 | |
---|
82 | #define L2C_310_MIN( a, b ) \ |
---|
83 | ((a < b) ? (a) : (b)) |
---|
84 | |
---|
85 | #define L2C_310_MAX_LOCKING_BYTES (4 * 1024) |
---|
86 | |
---|
87 | |
---|
88 | /* RTL release number as can be read from cache_id register */ |
---|
89 | #define L2C_310_RTL_RELEASE_R0_P0 0x0 |
---|
90 | #define L2C_310_RTL_RELEASE_R1_P0 0x2 |
---|
91 | #define L2C_310_RTL_RELEASE_R2_P0 0x4 |
---|
92 | #define L2C_310_RTL_RELEASE_R3_P0 0x5 |
---|
93 | #define L2C_310_RTL_RELEASE_R3_P1 0x6 |
---|
94 | #define L2C_310_RTL_RELEASE_R3_P2 0x8 |
---|
95 | #define L2C_310_RTL_RELEASE_R3_P3 0x9 |
---|
96 | |
---|
97 | #define BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) |
---|
98 | |
---|
99 | /** |
---|
100 | * @defgroup L2C-310_cache Cache Support |
---|
101 | * @ingroup arm_shared |
---|
102 | * @brief Cache Functions and Defitions |
---|
103 | * @{ |
---|
104 | */ |
---|
105 | |
---|
106 | |
---|
107 | /** |
---|
108 | * @brief L2CC Register Offsets |
---|
109 | */ |
---|
110 | typedef struct { |
---|
111 | /** @brief Cache ID */ |
---|
112 | uint32_t cache_id; |
---|
113 | #define L2C_310_ID_RTL_MASK 0x3f |
---|
114 | #define L2C_310_ID_PART_MASK ( 0xf << 6 ) |
---|
115 | #define L2C_310_ID_PART_L210 ( 1 << 6 ) |
---|
116 | #define L2C_310_ID_PART_L310 ( 3 << 6 ) |
---|
117 | #define L2C_310_ID_IMPL_MASK ( 0xff << 24 ) |
---|
118 | /** @brief Cache type */ |
---|
119 | uint32_t cache_type; |
---|
120 | /** @brief 1 if data banking implemented, 0 if not */ |
---|
121 | #define L2C_310_TYPE_DATA_BANKING_MASK 0x80000000 |
---|
122 | /** @brief 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 */ |
---|
123 | #define L2C_310_TYPE_CTYPE_MASK 0x1E000000 |
---|
124 | /** @brief y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. */ |
---|
125 | #define L2C_310_TYPE_CTYPE_SHIFT 25 |
---|
126 | /** @brief 1 for Harvard architecture, 0 for unified architecture */ |
---|
127 | #define L2C_310_TYPE_HARVARD_MASK 0x01000000 |
---|
128 | /** @brief Data cache way size = 2 Exp(value + 2) KB */ |
---|
129 | #define L2C_310_TYPE_SIZE_D_WAYS_MASK 0x00700000 |
---|
130 | #define L2C_310_TYPE_SIZE_D_WAYS_SHIFT 20 |
---|
131 | /** @brief Assoziativity aka number of data ways = (value * 8) + 8 */ |
---|
132 | #define L2C_310_TYPE_NUM_D_WAYS_MASK 0x00040000 |
---|
133 | #define L2C_310_TYPE_NUM_D_WAYS_SHIFT 18 |
---|
134 | /** @brief Data cache line length 00 - 32 */ |
---|
135 | #define L2C_310_TYPE_LENGTH_D_LINE_MASK 0x00003000 |
---|
136 | #define L2C_310_TYPE_LENGTH_D_LINE_SHIFT 12 |
---|
137 | #define L2C_310_TYPE_LENGTH_D_LINE_VAL_32 0x0 |
---|
138 | /** @brief Instruction cache way size = 2 Exp(value + 2) KB */ |
---|
139 | #define L2C_310_TYPE_SIZE_I_WAYS_MASK 0x00000700 |
---|
140 | #define L2C_310_TYPE_SIZE_I_WAYS_SHIFT 8 |
---|
141 | /** @brief Assoziativity aka number of instruction ways = (value * 8) + 8 */ |
---|
142 | #define L2C_310_TYPE_NUM_I_WAYS_MASK 0x00000040 |
---|
143 | #define L2C_310_TYPE_NUM_I_WAYS_SHIFT 6 |
---|
144 | /** @brief Instruction cache line length 00 - 32 */ |
---|
145 | #define L2C_310_TYPE_LENGTH_I_LINE_MASK 0x00000003 |
---|
146 | #define L2C_310_TYPE_LENGTH_I_LINE_SHIFT 0 |
---|
147 | #define L2C_310_TYPE_LENGTH_I_LINE_VAL_32 0x0 |
---|
148 | |
---|
149 | uint8_t reserved_8[0x100 - 8]; |
---|
150 | uint32_t ctrl; /* Control */ |
---|
151 | /** @brief Enables the L2CC */ |
---|
152 | #define L2C_310_CTRL_ENABLE 0x00000001 |
---|
153 | |
---|
154 | #define L2C_310_CTRL_EXCL_CONFIG (1 << 12) |
---|
155 | |
---|
156 | /** @brief Auxiliary control */ |
---|
157 | uint32_t aux_ctrl; |
---|
158 | |
---|
159 | /** @brief Early BRESP Enable */ |
---|
160 | #define L2C_310_AUX_EBRESPE_MASK 0x40000000 |
---|
161 | |
---|
162 | /** @brief Instruction Prefetch Enable */ |
---|
163 | #define L2C_310_AUX_IPFE_MASK 0x20000000 |
---|
164 | |
---|
165 | /** @brief Data Prefetch Enable */ |
---|
166 | #define L2C_310_AUX_DPFE_MASK 0x10000000 |
---|
167 | |
---|
168 | /** @brief Non-secure interrupt access control */ |
---|
169 | #define L2C_310_AUX_NSIC_MASK 0x08000000 |
---|
170 | |
---|
171 | /** @brief Non-secure lockdown enable */ |
---|
172 | #define L2C_310_AUX_NSLE_MASK 0x04000000 |
---|
173 | |
---|
174 | /** @brief Cache replacement policy */ |
---|
175 | #define L2C_310_AUX_CRP_MASK 0x02000000 |
---|
176 | |
---|
177 | /** @brief Force write allocate */ |
---|
178 | #define L2C_310_AUX_FWE_MASK 0x01800000 |
---|
179 | |
---|
180 | /** @brief Shared attribute override enable */ |
---|
181 | #define L2C_310_AUX_SAOE_MASK 0x00400000 |
---|
182 | |
---|
183 | /** @brief Parity enable */ |
---|
184 | #define L2C_310_AUX_PE_MASK 0x00200000 |
---|
185 | |
---|
186 | /** @brief Event monitor bus enable */ |
---|
187 | #define L2C_310_AUX_EMBE_MASK 0x00100000 |
---|
188 | |
---|
189 | /** @brief Way-size */ |
---|
190 | #define L2C_310_AUX_WAY_SIZE_MASK 0x000E0000 |
---|
191 | #define L2C_310_AUX_WAY_SIZE_SHIFT 17 |
---|
192 | |
---|
193 | /** @brief Way-size */ |
---|
194 | #define L2C_310_AUX_ASSOC_MASK 0x00010000 |
---|
195 | |
---|
196 | /** @brief Shared attribute invalidate enable */ |
---|
197 | #define L2C_310_AUX_SAIE_MASK 0x00002000 |
---|
198 | |
---|
199 | /** @brief Exclusive cache configuration */ |
---|
200 | #define L2C_310_AUX_EXCL_CACHE_MASK 0x00001000 |
---|
201 | |
---|
202 | /** @brief Store buffer device limitation Enable */ |
---|
203 | #define L2C_310_AUX_SBDLE_MASK 0x00000800 |
---|
204 | |
---|
205 | /** @brief High Priority for SO and Dev Reads Enable */ |
---|
206 | #define L2C_310_AUX_HPSODRE_MASK 0x00000400 |
---|
207 | |
---|
208 | /** @brief Full line of zero enable */ |
---|
209 | #define L2C_310_AUX_FLZE_MASK 0x00000001 |
---|
210 | |
---|
211 | /** @brief Enable all prefetching, */ |
---|
212 | #define L2C_310_AUX_REG_DEFAULT_MASK \ |
---|
213 | ( L2C_310_AUX_WAY_SIZE_MASK & ( 0x3 << L2C_310_AUX_WAY_SIZE_SHIFT ) ) \ |
---|
214 | | L2C_310_AUX_PE_MASK /* Prefetch enable */ \ |
---|
215 | | L2C_310_AUX_SAOE_MASK /* Shared attribute override enable */ \ |
---|
216 | | L2C_310_AUX_CRP_MASK /* Cache replacement policy */ \ |
---|
217 | | L2C_310_AUX_DPFE_MASK /* Data prefetch enable */ \ |
---|
218 | | L2C_310_AUX_IPFE_MASK /* Instruction prefetch enable */ \ |
---|
219 | | L2C_310_AUX_EBRESPE_MASK /* Early BRESP enable */ |
---|
220 | |
---|
221 | #define L2C_310_AUX_REG_ZERO_MASK 0xFFF1FFFF |
---|
222 | |
---|
223 | /** @brief 1 cycle of latency, there is no additional latency fot tag RAM */ |
---|
224 | #define L2C_310_RAM_1_CYCLE_LAT_VAL 0x00000000 |
---|
225 | /** @brief 2 cycles of latency for tag RAM */ |
---|
226 | #define L2C_310_RAM_2_CYCLE_LAT_VAL 0x00000001 |
---|
227 | /** @brief 3 cycles of latency for tag RAM */ |
---|
228 | #define L2C_310_RAM_3_CYCLE_LAT_VAL 0x00000002 |
---|
229 | /** @brief 4 cycles of latency for tag RAM */ |
---|
230 | #define L2C_310_RAM_4_CYCLE_LAT_VAL 0x00000003 |
---|
231 | /** @brief 5 cycles of latency for tag RAM */ |
---|
232 | #define L2C_310_RAM_5_CYCLE_LAT_VAL 0x00000004 |
---|
233 | /** @brief 6 cycles of latency for tag RAM */ |
---|
234 | #define L2C_310_RAM_6_CYCLE_LAT_VAL 0x00000005 |
---|
235 | /** @brief 7 cycles of latency for tag RAM */ |
---|
236 | #define L2C_310_RAM_7_CYCLE_LAT_VAL 0x00000006 |
---|
237 | /** @brief 8 cycles of latency for tag RAM */ |
---|
238 | #define L2C_310_RAM_8_CYCLE_LAT_VAL 0x00000007 |
---|
239 | /** @brief Shift left setup latency values by this value */ |
---|
240 | #define L2C_310_RAM_SETUP_SHIFT 0x00000000 |
---|
241 | /** @brief Shift left read latency values by this value */ |
---|
242 | #define L2C_310_RAM_READ_SHIFT 0x00000004 |
---|
243 | /** @brief Shift left write latency values by this value */ |
---|
244 | #define L2C_310_RAM_WRITE_SHIFT 0x00000008 |
---|
245 | /** @brief Mask for RAM setup latency */ |
---|
246 | #define L2C_310_RAM_SETUP_LAT_MASK 0x00000007 |
---|
247 | /** @brief Mask for RAM read latency */ |
---|
248 | #define L2C_310_RAM_READ_LAT_MASK 0x00000070 |
---|
249 | /** @brief Mask for RAM read latency */ |
---|
250 | #define L2C_310_RAM_WRITE_LAT_MASK 0x00000700 |
---|
251 | /** @brief Latency for tag RAM */ |
---|
252 | uint32_t tag_ram_ctrl; |
---|
253 | /* @brief Latency for tag RAM */ |
---|
254 | #define L2C_310_TAG_RAM_DEFAULT_LAT \ |
---|
255 | ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ |
---|
256 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ |
---|
257 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) |
---|
258 | /** @brief Latency for data RAM */ |
---|
259 | uint32_t data_ram_ctrl; |
---|
260 | /** @brief Latency for data RAM */ |
---|
261 | #define L2C_310_DATA_RAM_DEFAULT_MASK \ |
---|
262 | ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ |
---|
263 | | ( L2C_310_RAM_3_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ |
---|
264 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) |
---|
265 | |
---|
266 | uint8_t reserved_110[0x200 - 0x110]; |
---|
267 | |
---|
268 | /** @brief Event counter control */ |
---|
269 | uint32_t ev_ctrl; |
---|
270 | |
---|
271 | /** @brief Event counter 1 configuration */ |
---|
272 | uint32_t ev_cnt1_cfg; |
---|
273 | |
---|
274 | /** @brief Event counter 0 configuration */ |
---|
275 | uint32_t ev_cnt0_cfg; |
---|
276 | |
---|
277 | /** @brief Event counter 1 value */ |
---|
278 | uint32_t ev_cnt1; |
---|
279 | |
---|
280 | /** @brief Event counter 0 value */ |
---|
281 | uint32_t ev_cnt0; |
---|
282 | |
---|
283 | /** @brief Interrupt enable mask */ |
---|
284 | uint32_t int_mask; |
---|
285 | |
---|
286 | /** @brief Masked interrupt status (read-only)*/ |
---|
287 | uint32_t int_mask_status; |
---|
288 | |
---|
289 | /** @brief Unmasked interrupt status */ |
---|
290 | uint32_t int_raw_status; |
---|
291 | |
---|
292 | /** @brief Interrupt clear */ |
---|
293 | uint32_t int_clr; |
---|
294 | |
---|
295 | /** |
---|
296 | * @name Interrupt bit masks |
---|
297 | * |
---|
298 | * @{ |
---|
299 | */ |
---|
300 | |
---|
301 | /** @brief DECERR from L3 */ |
---|
302 | #define L2C_310_INT_DECERR_MASK 0x00000100 |
---|
303 | |
---|
304 | /** @brief SLVERR from L3 */ |
---|
305 | #define L2C_310_INT_SLVERR_MASK 0x00000080 |
---|
306 | |
---|
307 | /** @brief Error on L2 data RAM (Read) */ |
---|
308 | #define L2C_310_INT_ERRRD_MASK 0x00000040 |
---|
309 | |
---|
310 | /** @brief Error on L2 tag RAM (Read) */ |
---|
311 | #define L2C_310_INT_ERRRT_MASK 0x00000020 |
---|
312 | |
---|
313 | /** @brief Error on L2 data RAM (Write) */ |
---|
314 | #define L2C_310_INT_ERRWD_MASK 0x00000010 |
---|
315 | |
---|
316 | /** @brief Error on L2 tag RAM (Write) */ |
---|
317 | #define L2C_310_INT_ERRWT_MASK 0x00000008 |
---|
318 | |
---|
319 | /** @brief Parity Error on L2 data RAM (Read) */ |
---|
320 | #define L2C_310_INT_PARRD_MASK 0x00000004 |
---|
321 | |
---|
322 | /** @brief Parity Error on L2 tag RAM (Read) */ |
---|
323 | #define L2C_310_INT_PARRT_MASK 0x00000002 |
---|
324 | |
---|
325 | /** @brief Event Counter1/0 Overflow Increment */ |
---|
326 | #define L2C_310_INT_ECNTR_MASK 0x00000001 |
---|
327 | |
---|
328 | /** @} */ |
---|
329 | |
---|
330 | uint8_t reserved_224[0x730 - 0x224]; |
---|
331 | |
---|
332 | /** @brief Drain the STB */ |
---|
333 | uint32_t cache_sync; |
---|
334 | uint8_t reserved_734[0x740 - 0x734]; |
---|
335 | /** @brief ARM Errata 753970 for pl310-r3p0 */ |
---|
336 | uint32_t dummy_cache_sync_reg; |
---|
337 | uint8_t reserved_744[0x770 - 0x744]; |
---|
338 | |
---|
339 | /** @brief Invalidate line by PA */ |
---|
340 | uint32_t inv_pa; |
---|
341 | uint8_t reserved_774[0x77c - 0x774]; |
---|
342 | |
---|
343 | /** @brief Invalidate by Way */ |
---|
344 | uint32_t inv_way; |
---|
345 | uint8_t reserved_780[0x7b0 - 0x780]; |
---|
346 | |
---|
347 | /** @brief Clean Line by PA */ |
---|
348 | uint32_t clean_pa; |
---|
349 | uint8_t reserved_7b4[0x7b8 - 0x7b4]; |
---|
350 | |
---|
351 | /** @brief Clean Line by Set/Way */ |
---|
352 | uint32_t clean_index; |
---|
353 | |
---|
354 | /** @brief Clean by Way */ |
---|
355 | uint32_t clean_way; |
---|
356 | uint8_t reserved_7c0[0x7f0 - 0x7c0]; |
---|
357 | |
---|
358 | /** @brief Clean and Invalidate Line by PA */ |
---|
359 | uint32_t clean_inv_pa; |
---|
360 | uint8_t reserved_7f4[0x7f8 - 0x7f4]; |
---|
361 | |
---|
362 | /** @brief Clean and Invalidate Line by Set/Way */ |
---|
363 | uint32_t clean_inv_indx; |
---|
364 | |
---|
365 | /** @brief Clean and Invalidate by Way */ |
---|
366 | uint32_t clean_inv_way; |
---|
367 | |
---|
368 | /** @brief Data lock down 0 */ |
---|
369 | uint32_t d_lockdown_0; |
---|
370 | |
---|
371 | /** @brief Instruction lock down 0 */ |
---|
372 | uint32_t i_lockdown_0; |
---|
373 | |
---|
374 | /** @brief Data lock down 1 */ |
---|
375 | uint32_t d_lockdown_1; |
---|
376 | |
---|
377 | /** @brief Instruction lock down 1 */ |
---|
378 | uint32_t i_lockdown_1; |
---|
379 | |
---|
380 | /** @brief Data lock down 2 */ |
---|
381 | uint32_t d_lockdown_2; |
---|
382 | |
---|
383 | /** @brief Instruction lock down 2 */ |
---|
384 | uint32_t i_lockdown_2; |
---|
385 | |
---|
386 | /** @brief Data lock down 3 */ |
---|
387 | uint32_t d_lockdown_3; |
---|
388 | |
---|
389 | /** @brief Instruction lock down 3 */ |
---|
390 | uint32_t i_lockdown_3; |
---|
391 | |
---|
392 | /** @brief Data lock down 4 */ |
---|
393 | uint32_t d_lockdown_4; |
---|
394 | |
---|
395 | /** @brief Instruction lock down 4 */ |
---|
396 | uint32_t i_lockdown_4; |
---|
397 | |
---|
398 | /** @brief Data lock down 5 */ |
---|
399 | uint32_t d_lockdown_5; |
---|
400 | |
---|
401 | /** @brief Instruction lock down 5 */ |
---|
402 | uint32_t i_lockdown_5; |
---|
403 | |
---|
404 | /** @brief Data lock down 6 */ |
---|
405 | uint32_t d_lockdown_6; |
---|
406 | |
---|
407 | /** @brief Instruction lock down 6 */ |
---|
408 | uint32_t i_lockdown_6; |
---|
409 | |
---|
410 | /** @brief Data lock down 7 */ |
---|
411 | uint32_t d_lockdown_7; |
---|
412 | |
---|
413 | /** @brief Instruction lock down 7 */ |
---|
414 | uint32_t i_lockdown_7; |
---|
415 | |
---|
416 | uint8_t reserved_940[0x950 - 0x940]; |
---|
417 | |
---|
418 | /** @brief Lockdown by Line Enable */ |
---|
419 | uint32_t lock_line_en; |
---|
420 | |
---|
421 | /** @brief Cache lockdown by way */ |
---|
422 | uint32_t unlock_way; |
---|
423 | |
---|
424 | uint8_t reserved_958[0xc00 - 0x958]; |
---|
425 | |
---|
426 | /** @brief Address range redirect, part 1 */ |
---|
427 | uint32_t addr_filtering_start; |
---|
428 | |
---|
429 | /** @brief Address range redirect, part 2 */ |
---|
430 | uint32_t addr_filtering_end; |
---|
431 | |
---|
432 | /** @brief Address filtering valid bits*/ |
---|
433 | #define L2C_310_ADDR_FILTER_VALID_MASK 0xFFF00000 |
---|
434 | |
---|
435 | /** @brief Address filtering enable bit*/ |
---|
436 | #define L2C_310_ADDR_FILTER_ENABLE_MASK 0x00000001 |
---|
437 | |
---|
438 | uint8_t reserved_c08[0xf40 - 0xc08]; |
---|
439 | |
---|
440 | /** @brief Debug control */ |
---|
441 | uint32_t debug_ctrl; |
---|
442 | |
---|
443 | /** @brief Debug SPIDEN bit */ |
---|
444 | #define L2C_310_DEBUG_SPIDEN_MASK 0x00000004 |
---|
445 | |
---|
446 | /** @brief Debug DWB bit, forces write through */ |
---|
447 | #define L2C_310_DEBUG_DWB_MASK 0x00000002 |
---|
448 | |
---|
449 | /** @brief Debug DCL bit, disables cache line fill */ |
---|
450 | #define L2C_310_DEBUG_DCL_MASK 0x00000002 |
---|
451 | |
---|
452 | uint8_t reserved_f44[0xf60 - 0xf44]; |
---|
453 | |
---|
454 | /** @brief Purpose prefetch enables */ |
---|
455 | uint32_t prefetch_ctrl; |
---|
456 | /** @brief Prefetch offset */ |
---|
457 | #define L2C_310_PREFETCH_OFFSET_MASK 0x0000001F |
---|
458 | uint8_t reserved_f64[0xf80 - 0xf64]; |
---|
459 | |
---|
460 | /** @brief Purpose power controls */ |
---|
461 | uint32_t power_ctrl; |
---|
462 | } L2CC; |
---|
463 | |
---|
464 | rtems_interrupt_lock l2c_310_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER( |
---|
465 | "L2-310 cache controller" |
---|
466 | ); |
---|
467 | |
---|
468 | /* Errata table for the LC2 310 Level 2 cache from ARM. |
---|
469 | * Information taken from ARMs |
---|
470 | * "CoreLink controllers and peripherals |
---|
471 | * - System controllers |
---|
472 | * - L2C-310 Level 2 Cache Controller |
---|
473 | * - Revision r3p3 |
---|
474 | * - Software Developer Errata Notice |
---|
475 | * - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310), |
---|
476 | * r3 releases Software Developers Errata Notice" |
---|
477 | * Please see this document for more information on these erratas */ |
---|
478 | #if BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R3_P0 |
---|
479 | #define L2C_310_ERRATA_IS_APPLICABLE_753970 |
---|
480 | #endif |
---|
481 | |
---|
482 | static bool l2c_310_errata_is_applicable_727913( |
---|
483 | uint32_t rtl_release |
---|
484 | ) |
---|
485 | { |
---|
486 | bool is_applicable = false; |
---|
487 | |
---|
488 | switch ( rtl_release ) { |
---|
489 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
490 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
491 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
492 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
493 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
494 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
495 | is_applicable = false; |
---|
496 | break; |
---|
497 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
498 | is_applicable = true; |
---|
499 | break; |
---|
500 | default: |
---|
501 | assert( 0 ); |
---|
502 | break; |
---|
503 | } |
---|
504 | |
---|
505 | return is_applicable; |
---|
506 | } |
---|
507 | |
---|
508 | static bool l2c_310_errata_is_applicable_727914( |
---|
509 | uint32_t rtl_release |
---|
510 | ) |
---|
511 | { |
---|
512 | bool is_applicable = false; |
---|
513 | |
---|
514 | switch ( rtl_release ) { |
---|
515 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
516 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
517 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
518 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
519 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
520 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
521 | is_applicable = false; |
---|
522 | break; |
---|
523 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
524 | is_applicable = true; |
---|
525 | break; |
---|
526 | default: |
---|
527 | assert( 0 ); |
---|
528 | break; |
---|
529 | } |
---|
530 | |
---|
531 | return is_applicable; |
---|
532 | } |
---|
533 | |
---|
534 | static bool l2c_310_errata_is_applicable_727915( |
---|
535 | uint32_t rtl_release |
---|
536 | ) |
---|
537 | { |
---|
538 | bool is_applicable = false; |
---|
539 | |
---|
540 | switch ( rtl_release ) { |
---|
541 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
542 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
543 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
544 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
545 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
546 | is_applicable = false; |
---|
547 | break; |
---|
548 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
549 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
550 | is_applicable = true; |
---|
551 | break; |
---|
552 | default: |
---|
553 | assert( 0 ); |
---|
554 | break; |
---|
555 | } |
---|
556 | |
---|
557 | return is_applicable; |
---|
558 | } |
---|
559 | |
---|
560 | static bool l2c_310_errata_is_applicable_729806( |
---|
561 | uint32_t rtl_release |
---|
562 | ) |
---|
563 | { |
---|
564 | bool is_applicable = false; |
---|
565 | |
---|
566 | switch ( rtl_release ) { |
---|
567 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
568 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
569 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
570 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
571 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
572 | is_applicable = false; |
---|
573 | break; |
---|
574 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
575 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
576 | is_applicable = true; |
---|
577 | break; |
---|
578 | default: |
---|
579 | assert( 0 ); |
---|
580 | break; |
---|
581 | } |
---|
582 | |
---|
583 | return is_applicable; |
---|
584 | } |
---|
585 | |
---|
586 | static bool l2c_310_errata_is_applicable_729815( |
---|
587 | uint32_t rtl_release |
---|
588 | ) |
---|
589 | { |
---|
590 | bool is_applicable = false; |
---|
591 | |
---|
592 | switch ( rtl_release ) { |
---|
593 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
594 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
595 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
596 | is_applicable = false; |
---|
597 | break; |
---|
598 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
599 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
600 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
601 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
602 | is_applicable = true; |
---|
603 | break; |
---|
604 | default: |
---|
605 | assert( 0 ); |
---|
606 | break; |
---|
607 | } |
---|
608 | |
---|
609 | return is_applicable; |
---|
610 | } |
---|
611 | |
---|
612 | static bool l2c_310_errata_is_applicable_742884( |
---|
613 | uint32_t rtl_release |
---|
614 | ) |
---|
615 | { |
---|
616 | bool is_applicable = false; |
---|
617 | |
---|
618 | switch ( rtl_release ) { |
---|
619 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
620 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
621 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
622 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
623 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
624 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
625 | is_applicable = false; |
---|
626 | break; |
---|
627 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
628 | is_applicable = true; |
---|
629 | break; |
---|
630 | default: |
---|
631 | assert( 0 ); |
---|
632 | break; |
---|
633 | } |
---|
634 | |
---|
635 | return is_applicable; |
---|
636 | } |
---|
637 | |
---|
638 | static bool l2c_310_errata_is_applicable_752271( |
---|
639 | uint32_t rtl_release |
---|
640 | ) |
---|
641 | { |
---|
642 | bool is_applicable = false; |
---|
643 | |
---|
644 | switch ( rtl_release ) { |
---|
645 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
646 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
647 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
648 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
649 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
650 | is_applicable = false; |
---|
651 | break; |
---|
652 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
653 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
654 | is_applicable = true; |
---|
655 | break; |
---|
656 | default: |
---|
657 | assert( 0 ); |
---|
658 | break; |
---|
659 | } |
---|
660 | |
---|
661 | return is_applicable; |
---|
662 | } |
---|
663 | |
---|
664 | static bool l2c_310_errata_is_applicable_765569( |
---|
665 | uint32_t rtl_release |
---|
666 | ) |
---|
667 | { |
---|
668 | bool is_applicable = false; |
---|
669 | |
---|
670 | switch ( rtl_release ) { |
---|
671 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
672 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
673 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
674 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
675 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
676 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
677 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
678 | is_applicable = true; |
---|
679 | break; |
---|
680 | default: |
---|
681 | assert( 0 ); |
---|
682 | break; |
---|
683 | } |
---|
684 | |
---|
685 | return is_applicable; |
---|
686 | } |
---|
687 | |
---|
688 | static bool l2c_310_errata_is_applicable_769419( |
---|
689 | uint32_t rtl_release |
---|
690 | ) |
---|
691 | { |
---|
692 | bool is_applicable = false; |
---|
693 | |
---|
694 | switch ( rtl_release ) { |
---|
695 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
696 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
697 | is_applicable = false; |
---|
698 | break; |
---|
699 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
700 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
701 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
702 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
703 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
704 | is_applicable = true; |
---|
705 | break; |
---|
706 | default: |
---|
707 | assert( 0 ); |
---|
708 | break; |
---|
709 | } |
---|
710 | |
---|
711 | return is_applicable; |
---|
712 | } |
---|
713 | |
---|
714 | #if BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R0_P0 \ |
---|
715 | || BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R1_P0 |
---|
716 | #define L2C_310_ERRATA_IS_APPLICABLE_588369 |
---|
717 | #endif |
---|
718 | |
---|
719 | #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS |
---|
720 | static bool l2c_310_errata_is_applicable_754670( |
---|
721 | uint32_t rtl_release |
---|
722 | ) |
---|
723 | { |
---|
724 | bool is_applicable = false; |
---|
725 | |
---|
726 | switch ( rtl_release ) { |
---|
727 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
728 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
729 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
730 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
731 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
732 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
733 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
734 | is_applicable = true; |
---|
735 | break; |
---|
736 | default: |
---|
737 | assert( 0 ); |
---|
738 | break; |
---|
739 | } |
---|
740 | |
---|
741 | return is_applicable; |
---|
742 | } |
---|
743 | #endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */ |
---|
744 | |
---|
745 | /* The common workaround for this erratum would be to add a |
---|
746 | * data synchronization barrier to the beginning of the abort handler. |
---|
747 | * But for RTEMS a call of the abort handler means a fatal condition anyway. |
---|
748 | * So there is no need to handle this erratum */ |
---|
749 | #define CACHE_ARM_ERRATA_775420_HANDLER() \ |
---|
750 | if( arm_errata_is_applicable_processor_errata_775420 ) { \ |
---|
751 | } \ |
---|
752 | |
---|
753 | static void l2c_310_check_errata( uint32_t rtl_release ) |
---|
754 | { |
---|
755 | /* This erratum gets handled within the sources */ |
---|
756 | /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may |
---|
757 | * keep the cache line if it was clean. See ARMs documentation on the erratum |
---|
758 | * for a workaround */ |
---|
759 | /* assert( ! l2c_310_errata_is_applicable_588369( rtl_release ) ); */ |
---|
760 | |
---|
761 | /* Unhandled erratum present: 727913 Prefetch dropping feature can cause |
---|
762 | * incorrect behavior when PL310 handles reads that cross cache line |
---|
763 | * boundary */ |
---|
764 | assert( ! l2c_310_errata_is_applicable_727913( rtl_release ) ); |
---|
765 | |
---|
766 | /* Unhandled erratum present: 727914 Double linefill feature can cause |
---|
767 | * deadlock */ |
---|
768 | assert( ! l2c_310_errata_is_applicable_727914( rtl_release ) ); |
---|
769 | |
---|
770 | /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way |
---|
771 | * operation can cause data corruption */ |
---|
772 | assert( ! l2c_310_errata_is_applicable_727915( rtl_release ) ); |
---|
773 | |
---|
774 | /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 |
---|
775 | * MPCore processor can cause deadlock */ |
---|
776 | assert( ! l2c_310_errata_is_applicable_729806( rtl_release ) ); |
---|
777 | |
---|
778 | if( l2c_310_errata_is_applicable_729815( rtl_release ) ) |
---|
779 | { |
---|
780 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
781 | |
---|
782 | assert( 0 == ( l2cc->aux_ctrl & L2C_310_AUX_HPSODRE_MASK ) ); |
---|
783 | |
---|
784 | /* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can |
---|
785 | * cause Quality of Service issues to cacheable read transactions*/ |
---|
786 | |
---|
787 | /* Conditions |
---|
788 | This problem occurs when the following conditions are met: |
---|
789 | 1. Bit[10] âHigh Priority for SO and Dev reads enableâ of the PL310 |
---|
790 | Auxiliary Control Register is set to 1. |
---|
791 | 2. PL310 receives a cacheable read that misses in the L2 cache. |
---|
792 | 3. PL310 receives a continuous flow of Strongly Ordered or Device |
---|
793 | reads that take all address slots in the master interface. |
---|
794 | Workaround |
---|
795 | A workaround is only necessary in systems that are able to issue a |
---|
796 | continuous flow of Strongly Ordered or Device reads. In such a case, |
---|
797 | the workaround is to disable the âHigh Priority for SO and Dev readsâ |
---|
798 | feature. This is the default behavior.*/ |
---|
799 | } |
---|
800 | |
---|
801 | /* Unhandled erratum present: 742884 Double linefill feature might introduce |
---|
802 | * circular dependency and deadlock */ |
---|
803 | assert( ! l2c_310_errata_is_applicable_742884( rtl_release ) ); |
---|
804 | |
---|
805 | /* Unhandled erratum present: 752271 Double linefill feature can cause data |
---|
806 | * corruption */ |
---|
807 | assert( ! l2c_310_errata_is_applicable_752271( rtl_release ) ); |
---|
808 | |
---|
809 | /* This erratum can not be worked around: 754670 A continuous write flow can |
---|
810 | * stall a read targeting the same memory area |
---|
811 | * But this erratum does not lead to any data corruption */ |
---|
812 | /* assert( ! l2c_310_errata_is_applicable_754670() ); */ |
---|
813 | |
---|
814 | if( l2c_310_errata_is_applicable_765569( rtl_release ) ) |
---|
815 | { |
---|
816 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
817 | |
---|
818 | assert( !( ( l2cc->aux_ctrl & L2C_310_AUX_IPFE_MASK |
---|
819 | || l2cc->aux_ctrl & L2C_310_AUX_DPFE_MASK ) |
---|
820 | && ( ( l2cc->prefetch_ctrl & L2C_310_PREFETCH_OFFSET_MASK ) |
---|
821 | == 23 ) ) ); |
---|
822 | |
---|
823 | /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if |
---|
824 | * offset is programmed with value 23 */ |
---|
825 | |
---|
826 | /* Conditions |
---|
827 | This problem occurs when the following conditions are met: |
---|
828 | 1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or |
---|
829 | Prefetch Control Register) is set HIGH. |
---|
830 | 2. The prefetch offset bits are programmed with value 23 (5'b10111). |
---|
831 | Workaround |
---|
832 | A workaround for this erratum is to program the prefetch offset with any |
---|
833 | value except 23.*/ |
---|
834 | } |
---|
835 | |
---|
836 | /* Unhandled erratum present: 769419 No automatic Store Buffer drain, |
---|
837 | * visibility of written data requires an explicit Cache */ |
---|
838 | assert( ! l2c_310_errata_is_applicable_769419( rtl_release ) ); |
---|
839 | } |
---|
840 | |
---|
841 | static inline void |
---|
842 | l2c_310_sync( volatile L2CC *l2cc ) |
---|
843 | { |
---|
844 | #ifdef L2C_310_ERRATA_IS_APPLICABLE_753970 |
---|
845 | l2cc->dummy_cache_sync_reg = 0; |
---|
846 | #else |
---|
847 | l2cc->cache_sync = 0; |
---|
848 | #endif |
---|
849 | } |
---|
850 | |
---|
851 | static inline void |
---|
852 | l2c_310_flush_1_line( volatile L2CC *l2cc, uint32_t d_addr ) |
---|
853 | { |
---|
854 | #ifdef L2C_310_ERRATA_IS_APPLICABLE_588369 |
---|
855 | /* |
---|
856 | * Errata 588369 says that clean + inv may keep the |
---|
857 | * cache line if it was clean, the recommended |
---|
858 | * workaround is to clean then invalidate the cache |
---|
859 | * line, with write-back and cache linefill disabled. |
---|
860 | */ |
---|
861 | l2cc->clean_pa = d_addr; |
---|
862 | l2c_310_sync( l2cc ); |
---|
863 | l2cc->inv_pa = d_addr; |
---|
864 | #else |
---|
865 | l2cc->clean_inv_pa = d_addr; |
---|
866 | #endif |
---|
867 | } |
---|
868 | |
---|
869 | static inline void |
---|
870 | l2c_310_flush_range( const void* d_addr, const size_t n_bytes ) |
---|
871 | { |
---|
872 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
873 | uint32_t adx = (uint32_t)d_addr |
---|
874 | & ~L2C_310_DATA_LINE_MASK; |
---|
875 | const uint32_t ADDR_LAST = |
---|
876 | (uint32_t)( (size_t)d_addr + n_bytes - 1 ); |
---|
877 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
878 | |
---|
879 | if ( n_bytes == 0 ) { |
---|
880 | return; |
---|
881 | } |
---|
882 | |
---|
883 | for (; adx <= ADDR_LAST; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
---|
884 | l2c_310_flush_1_line( l2cc, adx ); |
---|
885 | } |
---|
886 | |
---|
887 | l2c_310_sync( l2cc ); |
---|
888 | } |
---|
889 | |
---|
890 | static inline void |
---|
891 | l2c_310_flush_entire( void ) |
---|
892 | { |
---|
893 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
894 | rtems_interrupt_lock_context lock_context; |
---|
895 | |
---|
896 | /* Only flush if level 2 cache is active */ |
---|
897 | if( ( l2cc->ctrl & L2C_310_CTRL_ENABLE ) != 0 ) { |
---|
898 | |
---|
899 | /* ensure ordering with previous memory accesses */ |
---|
900 | _ARM_Data_memory_barrier(); |
---|
901 | |
---|
902 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
---|
903 | l2cc->clean_inv_way = L2C_310_WAY_MASK; |
---|
904 | |
---|
905 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) {}; |
---|
906 | |
---|
907 | /* Wait for the flush to complete */ |
---|
908 | l2c_310_sync( l2cc ); |
---|
909 | |
---|
910 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
911 | } |
---|
912 | } |
---|
913 | |
---|
914 | static inline void |
---|
915 | l2c_310_invalidate_1_line( const void *d_addr ) |
---|
916 | { |
---|
917 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
918 | |
---|
919 | |
---|
920 | l2cc->inv_pa = (uint32_t) d_addr; |
---|
921 | l2c_310_sync( l2cc ); |
---|
922 | } |
---|
923 | |
---|
924 | static inline void |
---|
925 | l2c_310_invalidate_range( const void* d_addr, const size_t n_bytes ) |
---|
926 | { |
---|
927 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
928 | uint32_t adx = (uint32_t)d_addr |
---|
929 | & ~L2C_310_DATA_LINE_MASK; |
---|
930 | const uint32_t ADDR_LAST = |
---|
931 | (uint32_t)( (size_t)d_addr + n_bytes - 1 ); |
---|
932 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
933 | |
---|
934 | if ( n_bytes == 0 ) { |
---|
935 | return; |
---|
936 | } |
---|
937 | |
---|
938 | for (; adx <= ADDR_LAST; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
---|
939 | /* Invalidate L2 cache line */ |
---|
940 | l2cc->inv_pa = adx; |
---|
941 | } |
---|
942 | |
---|
943 | l2c_310_sync( l2cc ); |
---|
944 | } |
---|
945 | |
---|
946 | |
---|
947 | static inline void |
---|
948 | l2c_310_invalidate_entire( void ) |
---|
949 | { |
---|
950 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
951 | |
---|
952 | /* Invalidate the caches */ |
---|
953 | |
---|
954 | /* ensure ordering with previous memory accesses */ |
---|
955 | _ARM_Data_memory_barrier(); |
---|
956 | |
---|
957 | l2cc->inv_way = L2C_310_WAY_MASK; |
---|
958 | |
---|
959 | while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; |
---|
960 | |
---|
961 | /* Wait for the invalidate to complete */ |
---|
962 | l2c_310_sync( l2cc ); |
---|
963 | } |
---|
964 | |
---|
965 | static inline void |
---|
966 | l2c_310_clean_and_invalidate_entire( void ) |
---|
967 | { |
---|
968 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
969 | rtems_interrupt_lock_context lock_context; |
---|
970 | |
---|
971 | if( ( l2cc->ctrl & L2C_310_CTRL_ENABLE ) != 0 ) { |
---|
972 | /* Invalidate the caches */ |
---|
973 | |
---|
974 | /* ensure ordering with previous memory accesses */ |
---|
975 | _ARM_Data_memory_barrier(); |
---|
976 | |
---|
977 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
---|
978 | l2cc->clean_inv_way = L2C_310_WAY_MASK; |
---|
979 | |
---|
980 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; |
---|
981 | |
---|
982 | /* Wait for the invalidate to complete */ |
---|
983 | l2c_310_sync( l2cc ); |
---|
984 | |
---|
985 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
986 | } |
---|
987 | } |
---|
988 | |
---|
989 | static inline void |
---|
990 | l2c_310_freeze( void ) |
---|
991 | { |
---|
992 | /* To be implemented as needed, if supported |
---|
993 | by hardware at all */ |
---|
994 | } |
---|
995 | |
---|
996 | static inline void |
---|
997 | l2c_310_unfreeze( void ) |
---|
998 | { |
---|
999 | /* To be implemented as needed, if supported |
---|
1000 | by hardware at all */ |
---|
1001 | } |
---|
1002 | |
---|
1003 | static inline size_t |
---|
1004 | l2c_310_get_cache_size( void ) |
---|
1005 | { |
---|
1006 | size_t size = 0; |
---|
1007 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1008 | uint32_t cache_type = l2cc->cache_type; |
---|
1009 | uint32_t way_size; |
---|
1010 | uint32_t num_ways; |
---|
1011 | |
---|
1012 | way_size = (cache_type & L2C_310_TYPE_SIZE_D_WAYS_MASK) |
---|
1013 | >> L2C_310_TYPE_SIZE_D_WAYS_SHIFT; |
---|
1014 | num_ways = (cache_type & L2C_310_TYPE_NUM_D_WAYS_MASK) |
---|
1015 | >> L2C_310_TYPE_NUM_D_WAYS_SHIFT; |
---|
1016 | |
---|
1017 | assert( way_size <= 0x07 ); |
---|
1018 | assert( num_ways <= 0x01 ); |
---|
1019 | if( way_size <= 0x07 && num_ways <= 0x01 ) { |
---|
1020 | if( way_size == 0x00 ) { |
---|
1021 | way_size = 16 * 1024; |
---|
1022 | } else if( way_size == 0x07 ) { |
---|
1023 | way_size = 512 * 1024; |
---|
1024 | } else { |
---|
1025 | way_size = (1 << (way_size - 1)) * 16 * 1024; |
---|
1026 | } |
---|
1027 | switch( num_ways ) { |
---|
1028 | case 0: |
---|
1029 | num_ways = 8; |
---|
1030 | break; |
---|
1031 | case 1: |
---|
1032 | num_ways = 16; |
---|
1033 | break; |
---|
1034 | default: |
---|
1035 | num_ways = 0; |
---|
1036 | break; |
---|
1037 | } |
---|
1038 | size = way_size * num_ways; |
---|
1039 | } |
---|
1040 | return size; |
---|
1041 | } |
---|
1042 | |
---|
1043 | static void l2c_310_unlock( volatile L2CC *l2cc ) |
---|
1044 | { |
---|
1045 | l2cc->d_lockdown_0 = 0; |
---|
1046 | l2cc->i_lockdown_0 = 0; |
---|
1047 | l2cc->d_lockdown_1 = 0; |
---|
1048 | l2cc->i_lockdown_1 = 0; |
---|
1049 | l2cc->d_lockdown_2 = 0; |
---|
1050 | l2cc->i_lockdown_2 = 0; |
---|
1051 | l2cc->d_lockdown_3 = 0; |
---|
1052 | l2cc->i_lockdown_3 = 0; |
---|
1053 | l2cc->d_lockdown_4 = 0; |
---|
1054 | l2cc->i_lockdown_4 = 0; |
---|
1055 | l2cc->d_lockdown_5 = 0; |
---|
1056 | l2cc->i_lockdown_5 = 0; |
---|
1057 | l2cc->d_lockdown_6 = 0; |
---|
1058 | l2cc->i_lockdown_6 = 0; |
---|
1059 | l2cc->d_lockdown_7 = 0; |
---|
1060 | l2cc->i_lockdown_7 = 0; |
---|
1061 | } |
---|
1062 | |
---|
1063 | static void l2c_310_wait_for_background_ops( volatile L2CC *l2cc ) |
---|
1064 | { |
---|
1065 | while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; |
---|
1066 | |
---|
1067 | while ( l2cc->clean_way & L2C_310_WAY_MASK ) ; |
---|
1068 | |
---|
1069 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; |
---|
1070 | } |
---|
1071 | |
---|
1072 | /* We support only the L2C-310 revisions r3p2 and r3p3 cache controller */ |
---|
1073 | |
---|
1074 | #if (BSP_ARM_L2C_310_ID & L2C_310_ID_PART_MASK) \ |
---|
1075 | != L2C_310_ID_PART_L310 |
---|
1076 | #error "invalid L2-310 cache controller part number" |
---|
1077 | #endif |
---|
1078 | |
---|
1079 | #if (BSP_ARM_L2C_310_RTL_RELEASE != L2C_310_RTL_RELEASE_R3_P2) \ |
---|
1080 | && (BSP_ARM_L2C_310_RTL_RELEASE != L2C_310_RTL_RELEASE_R3_P3) |
---|
1081 | #error "invalid L2-310 cache controller RTL revision" |
---|
1082 | #endif |
---|
1083 | |
---|
1084 | static inline void |
---|
1085 | l2c_310_enable( void ) |
---|
1086 | { |
---|
1087 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1088 | uint32_t cache_id = l2cc->cache_id; |
---|
1089 | uint32_t rtl_release = cache_id & L2C_310_ID_RTL_MASK; |
---|
1090 | uint32_t id_mask = L2C_310_ID_IMPL_MASK | L2C_310_ID_PART_MASK; |
---|
1091 | uint32_t ctrl; |
---|
1092 | |
---|
1093 | /* |
---|
1094 | * Do we actually have an L2C-310 cache controller? Has BSP_ARM_L2C_310_BASE |
---|
1095 | * been configured correctly? |
---|
1096 | */ |
---|
1097 | if ( |
---|
1098 | (BSP_ARM_L2C_310_ID & id_mask) != (cache_id & id_mask) |
---|
1099 | || rtl_release < BSP_ARM_L2C_310_RTL_RELEASE |
---|
1100 | ) { |
---|
1101 | bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_ID ); |
---|
1102 | } |
---|
1103 | |
---|
1104 | l2c_310_check_errata( rtl_release ); |
---|
1105 | |
---|
1106 | ctrl = l2cc->ctrl; |
---|
1107 | |
---|
1108 | if ( ( ctrl & L2C_310_CTRL_EXCL_CONFIG ) != 0 ) { |
---|
1109 | bsp_fatal( ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG ); |
---|
1110 | } |
---|
1111 | |
---|
1112 | /* Only enable if L2CC is currently disabled */ |
---|
1113 | if( ( ctrl & L2C_310_CTRL_ENABLE ) == 0 ) { |
---|
1114 | uint32_t aux_ctrl; |
---|
1115 | int ways; |
---|
1116 | |
---|
1117 | /* Make sure that I&D is not locked down when starting */ |
---|
1118 | l2c_310_unlock( l2cc ); |
---|
1119 | |
---|
1120 | l2c_310_wait_for_background_ops( l2cc ); |
---|
1121 | |
---|
1122 | aux_ctrl = l2cc->aux_ctrl; |
---|
1123 | |
---|
1124 | if ( (aux_ctrl & ( 1 << 16 )) != 0 ) { |
---|
1125 | ways = 16; |
---|
1126 | } else { |
---|
1127 | ways = 8; |
---|
1128 | } |
---|
1129 | |
---|
1130 | if ( ways != L2C_310_NUM_WAYS ) { |
---|
1131 | bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS ); |
---|
1132 | } |
---|
1133 | |
---|
1134 | /* Set up the way size */ |
---|
1135 | aux_ctrl &= L2C_310_AUX_REG_ZERO_MASK; /* Set way_size to 0 */ |
---|
1136 | aux_ctrl |= L2C_310_AUX_REG_DEFAULT_MASK; |
---|
1137 | |
---|
1138 | l2cc->aux_ctrl = aux_ctrl; |
---|
1139 | |
---|
1140 | /* Set up the latencies */ |
---|
1141 | l2cc->tag_ram_ctrl = L2C_310_TAG_RAM_DEFAULT_LAT; |
---|
1142 | l2cc->data_ram_ctrl = L2C_310_DATA_RAM_DEFAULT_MASK; |
---|
1143 | |
---|
1144 | l2c_310_invalidate_entire(); |
---|
1145 | |
---|
1146 | /* Clear the pending interrupts */ |
---|
1147 | l2cc->int_clr = l2cc->int_raw_status; |
---|
1148 | |
---|
1149 | /* Enable the L2CC */ |
---|
1150 | l2cc->ctrl = ctrl | L2C_310_CTRL_ENABLE; |
---|
1151 | } |
---|
1152 | } |
---|
1153 | |
---|
1154 | static inline void |
---|
1155 | l2c_310_disable( void ) |
---|
1156 | { |
---|
1157 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1158 | rtems_interrupt_lock_context lock_context; |
---|
1159 | |
---|
1160 | if ( l2cc->ctrl & L2C_310_CTRL_ENABLE ) { |
---|
1161 | /* Clean and Invalidate L2 Cache */ |
---|
1162 | l2c_310_flush_entire(); |
---|
1163 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
---|
1164 | |
---|
1165 | l2c_310_wait_for_background_ops( l2cc ); |
---|
1166 | |
---|
1167 | /* Disable the L2 cache */ |
---|
1168 | l2cc->ctrl &= ~L2C_310_CTRL_ENABLE; |
---|
1169 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
1170 | } |
---|
1171 | } |
---|
1172 | |
---|
1173 | static inline void |
---|
1174 | _CPU_cache_enable_data( void ) |
---|
1175 | { |
---|
1176 | l2c_310_enable(); |
---|
1177 | } |
---|
1178 | |
---|
1179 | static inline void |
---|
1180 | _CPU_cache_disable_data( void ) |
---|
1181 | { |
---|
1182 | arm_cache_l1_disable_data(); |
---|
1183 | l2c_310_disable(); |
---|
1184 | } |
---|
1185 | |
---|
1186 | static inline void |
---|
1187 | _CPU_cache_enable_instruction( void ) |
---|
1188 | { |
---|
1189 | l2c_310_enable(); |
---|
1190 | } |
---|
1191 | |
---|
1192 | static inline void |
---|
1193 | _CPU_cache_disable_instruction( void ) |
---|
1194 | { |
---|
1195 | arm_cache_l1_disable_instruction(); |
---|
1196 | l2c_310_disable(); |
---|
1197 | } |
---|
1198 | |
---|
1199 | static inline void |
---|
1200 | _CPU_cache_flush_data_range( |
---|
1201 | const void *d_addr, |
---|
1202 | size_t n_bytes |
---|
1203 | ) |
---|
1204 | { |
---|
1205 | arm_cache_l1_flush_data_range( |
---|
1206 | d_addr, |
---|
1207 | n_bytes |
---|
1208 | ); |
---|
1209 | l2c_310_flush_range( |
---|
1210 | d_addr, |
---|
1211 | n_bytes |
---|
1212 | ); |
---|
1213 | } |
---|
1214 | |
---|
1215 | static inline void |
---|
1216 | _CPU_cache_flush_entire_data( void ) |
---|
1217 | { |
---|
1218 | arm_cache_l1_flush_entire_data(); |
---|
1219 | l2c_310_flush_entire(); |
---|
1220 | } |
---|
1221 | |
---|
1222 | static inline void |
---|
1223 | _CPU_cache_invalidate_data_range( |
---|
1224 | const void *addr_first, |
---|
1225 | size_t n_bytes |
---|
1226 | ) |
---|
1227 | { |
---|
1228 | l2c_310_invalidate_range( |
---|
1229 | addr_first, |
---|
1230 | n_bytes |
---|
1231 | ); |
---|
1232 | arm_cache_l1_invalidate_data_range( |
---|
1233 | addr_first, |
---|
1234 | n_bytes |
---|
1235 | ); |
---|
1236 | } |
---|
1237 | |
---|
1238 | static inline void |
---|
1239 | _CPU_cache_invalidate_entire_data( void ) |
---|
1240 | { |
---|
1241 | /* This is broadcast within the cluster */ |
---|
1242 | arm_cache_l1_flush_entire_data(); |
---|
1243 | |
---|
1244 | /* forces the address out past level 2 */ |
---|
1245 | l2c_310_clean_and_invalidate_entire(); |
---|
1246 | |
---|
1247 | /*This is broadcast within the cluster */ |
---|
1248 | arm_cache_l1_clean_and_invalidate_entire_data(); |
---|
1249 | } |
---|
1250 | |
---|
1251 | static inline void |
---|
1252 | _CPU_cache_freeze_data( void ) |
---|
1253 | { |
---|
1254 | arm_cache_l1_freeze_data(); |
---|
1255 | l2c_310_freeze(); |
---|
1256 | } |
---|
1257 | |
---|
1258 | static inline void |
---|
1259 | _CPU_cache_unfreeze_data( void ) |
---|
1260 | { |
---|
1261 | arm_cache_l1_unfreeze_data(); |
---|
1262 | l2c_310_unfreeze(); |
---|
1263 | } |
---|
1264 | |
---|
1265 | static inline void |
---|
1266 | _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes) |
---|
1267 | { |
---|
1268 | arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes ); |
---|
1269 | } |
---|
1270 | |
---|
1271 | static inline void |
---|
1272 | _CPU_cache_invalidate_entire_instruction( void ) |
---|
1273 | { |
---|
1274 | arm_cache_l1_invalidate_entire_instruction(); |
---|
1275 | } |
---|
1276 | |
---|
1277 | static inline void |
---|
1278 | _CPU_cache_freeze_instruction( void ) |
---|
1279 | { |
---|
1280 | arm_cache_l1_freeze_instruction(); |
---|
1281 | l2c_310_freeze(); |
---|
1282 | } |
---|
1283 | |
---|
1284 | static inline void |
---|
1285 | _CPU_cache_unfreeze_instruction( void ) |
---|
1286 | { |
---|
1287 | arm_cache_l1_unfreeze_instruction(); |
---|
1288 | l2c_310_unfreeze(); |
---|
1289 | } |
---|
1290 | |
---|
1291 | static inline size_t |
---|
1292 | _CPU_cache_get_data_cache_size( const uint32_t level ) |
---|
1293 | { |
---|
1294 | size_t size = 0; |
---|
1295 | |
---|
1296 | switch( level ) |
---|
1297 | { |
---|
1298 | case 1: |
---|
1299 | size = arm_cache_l1_get_data_cache_size(); |
---|
1300 | break; |
---|
1301 | case 0: |
---|
1302 | case 2: |
---|
1303 | size = l2c_310_get_cache_size(); |
---|
1304 | break; |
---|
1305 | default: |
---|
1306 | size = 0; |
---|
1307 | break; |
---|
1308 | } |
---|
1309 | return size; |
---|
1310 | } |
---|
1311 | |
---|
1312 | static inline size_t |
---|
1313 | _CPU_cache_get_instruction_cache_size( const uint32_t level ) |
---|
1314 | { |
---|
1315 | size_t size = 0; |
---|
1316 | |
---|
1317 | switch( level ) |
---|
1318 | { |
---|
1319 | case 1: |
---|
1320 | size = arm_cache_l1_get_instruction_cache_size(); |
---|
1321 | break; |
---|
1322 | case 0: |
---|
1323 | case 2: |
---|
1324 | size = l2c_310_get_cache_size(); |
---|
1325 | break; |
---|
1326 | default: |
---|
1327 | size = 0; |
---|
1328 | break; |
---|
1329 | } |
---|
1330 | return size; |
---|
1331 | } |
---|
1332 | |
---|
1333 | #include "../../shared/cache/cacheimpl.h" |
---|