1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm |
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5 | * |
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6 | * @brief ARM cache defines and implementation. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <libcpu/arm-cp15.h> |
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24 | #include "cache-cp15.h" |
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25 | |
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26 | #define CPU_DATA_CACHE_ALIGNMENT 32 |
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27 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 |
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28 | #if defined(__ARM_ARCH_7A__) |
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29 | /* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */ |
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30 | #define CPU_MAXIMAL_CACHE_ALIGNMENT 64 |
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31 | #endif |
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32 | |
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33 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ |
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34 | ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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35 | |
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36 | |
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37 | static inline void _CPU_cache_flush_1_data_line(const void *d_addr) |
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38 | { |
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39 | arm_cache_l1_flush_1_data_line(d_addr); |
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40 | } |
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41 | |
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42 | static inline void |
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43 | _CPU_cache_flush_data_range( |
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44 | const void *d_addr, |
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45 | size_t n_bytes |
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46 | ) |
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47 | { |
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48 | _ARM_Data_synchronization_barrier(); |
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49 | arm_cache_l1_flush_data_range( |
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50 | d_addr, |
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51 | n_bytes |
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52 | ); |
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53 | #if !defined(__ARM_ARCH_7A__) |
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54 | arm_cp15_drain_write_buffer(); |
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55 | #endif |
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56 | _ARM_Data_synchronization_barrier(); |
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57 | } |
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58 | |
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59 | static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr) |
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60 | { |
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61 | arm_cache_l1_invalidate_1_data_line(d_addr); |
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62 | } |
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63 | |
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64 | static inline void |
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65 | _CPU_cache_invalidate_data_range( |
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66 | const void *addr_first, |
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67 | size_t n_bytes |
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68 | ) |
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69 | { |
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70 | arm_cache_l1_invalidate_data_range( |
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71 | addr_first, |
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72 | n_bytes |
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73 | ); |
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74 | } |
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75 | |
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76 | static inline void _CPU_cache_freeze_data(void) |
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77 | { |
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78 | /* TODO */ |
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79 | } |
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80 | |
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81 | static inline void _CPU_cache_unfreeze_data(void) |
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82 | { |
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83 | /* TODO */ |
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84 | } |
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85 | |
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86 | static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) |
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87 | { |
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88 | arm_cache_l1_invalidate_1_instruction_line(d_addr); |
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89 | } |
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90 | |
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91 | static inline void |
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92 | _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes) |
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93 | { |
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94 | arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes ); |
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95 | _ARM_Instruction_synchronization_barrier(); |
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96 | } |
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97 | |
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98 | static inline void _CPU_cache_freeze_instruction(void) |
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99 | { |
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100 | /* TODO */ |
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101 | } |
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102 | |
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103 | static inline void _CPU_cache_unfreeze_instruction(void) |
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104 | { |
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105 | /* TODO */ |
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106 | } |
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107 | |
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108 | static inline void _CPU_cache_flush_entire_data(void) |
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109 | { |
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110 | _ARM_Data_synchronization_barrier(); |
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111 | #if defined(__ARM_ARCH_7A__) |
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112 | arm_cp15_data_cache_clean_all_levels(); |
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113 | #else |
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114 | arm_cp15_data_cache_clean_and_invalidate(); |
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115 | arm_cp15_drain_write_buffer(); |
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116 | #endif |
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117 | _ARM_Data_synchronization_barrier(); |
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118 | } |
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119 | |
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120 | static inline void _CPU_cache_invalidate_entire_data(void) |
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121 | { |
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122 | #if defined(__ARM_ARCH_7A__) |
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123 | arm_cp15_data_cache_invalidate_all_levels(); |
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124 | #else |
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125 | arm_cp15_data_cache_invalidate(); |
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126 | #endif |
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127 | } |
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128 | |
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129 | static inline void _CPU_cache_enable_data(void) |
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130 | { |
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131 | rtems_interrupt_level level; |
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132 | uint32_t ctrl; |
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133 | |
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134 | rtems_interrupt_local_disable(level); |
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135 | ctrl = arm_cp15_get_control(); |
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136 | ctrl |= ARM_CP15_CTRL_C; |
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137 | arm_cp15_set_control(ctrl); |
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138 | rtems_interrupt_local_enable(level); |
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139 | } |
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140 | |
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141 | static inline void _CPU_cache_disable_data(void) |
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142 | { |
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143 | rtems_interrupt_level level; |
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144 | uint32_t ctrl; |
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145 | |
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146 | rtems_interrupt_local_disable(level); |
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147 | arm_cp15_data_cache_test_and_clean_and_invalidate(); |
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148 | ctrl = arm_cp15_get_control(); |
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149 | ctrl &= ~ARM_CP15_CTRL_C; |
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150 | arm_cp15_set_control(ctrl); |
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151 | rtems_interrupt_local_enable(level); |
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152 | } |
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153 | |
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154 | static inline void _CPU_cache_invalidate_entire_instruction(void) |
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155 | { |
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156 | arm_cache_l1_invalidate_entire_instruction(); |
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157 | _ARM_Instruction_synchronization_barrier(); |
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158 | } |
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159 | |
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160 | static inline void _CPU_cache_enable_instruction(void) |
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161 | { |
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162 | rtems_interrupt_level level; |
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163 | uint32_t ctrl; |
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164 | |
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165 | rtems_interrupt_local_disable(level); |
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166 | ctrl = arm_cp15_get_control(); |
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167 | ctrl |= ARM_CP15_CTRL_I; |
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168 | arm_cp15_set_control(ctrl); |
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169 | rtems_interrupt_local_enable(level); |
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170 | } |
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171 | |
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172 | static inline void _CPU_cache_disable_instruction(void) |
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173 | { |
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174 | rtems_interrupt_level level; |
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175 | uint32_t ctrl; |
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176 | |
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177 | rtems_interrupt_local_disable(level); |
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178 | ctrl = arm_cp15_get_control(); |
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179 | ctrl &= ~ARM_CP15_CTRL_I; |
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180 | arm_cp15_set_control(ctrl); |
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181 | rtems_interrupt_local_enable(level); |
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182 | } |
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183 | |
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184 | #include "../../shared/cache/cacheimpl.h" |
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