source: rtems/bsps/arm/rtl22xx/start/start.S @ ff081aee

Last change on this file since ff081aee was ff081aee, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 6, 2018 at 3:58:02 PM

score: Rename interrupt stack symbols

Rename

  • _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
  • _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
  • _Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.

Update #3459.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Philips LPC22XX/LPC21xx Startup code
3 *
4 * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com>
5 * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com>
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9*/
10
11#include <rtems/asm.h>
12#include <rtems/score/cpu.h>
13
14.text
15.code   32
16.globl  _start
17_start:
18        /*
19         * Since I don't plan to return to the bootloader,
20         * I don't have to save the registers.
21         */
22
23        /* Set end of interrupt stack area */
24        ldr     r7, =_ISR_Stack_area_end
25
26        /* Enter FIQ mode and set up the FIQ stack pointer */
27        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
28        msr     cpsr, r0
29        ldr     r1, =bsp_stack_fiq_size
30        mov     sp, r7
31        sub     r7, r7, r1
32
33        /* Enter ABT mode and set up the ABT stack pointer */
34        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
35        msr     cpsr, r0
36        ldr     r1, =bsp_stack_abt_size
37        mov     sp, r7
38        sub     r7, r7, r1
39
40        /* Enter UND mode and set up the UND stack pointer */
41        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
42        msr     cpsr, r0
43        ldr     r1, =bsp_stack_und_size
44        mov     sp, r7
45        sub     r7, r7, r1
46
47        /* Enter IRQ mode and set up the IRQ stack pointer */
48        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
49        msr     cpsr, r0
50        mov     sp, r7
51
52        /*
53         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
54         * (interrupts are disabled).
55         */
56        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
57        msr     cpsr, r0
58        mov     sp, r7
59
60        /* Stay in SVC mode */
61
62        /*
63         * Initialize the exception vectors. This includes the
64         * exceptions vectors (0x00000000-0x0000001c), and the
65         * pointers to the exception handlers (0x00000020-0x0000003c).
66         */
67        mov     r0, #0
68        adr     r1, vector_block
69        ldmia   r1!, {r2-r9}
70        stmia   r0!, {r2-r9}
71
72        ldmia   r1!, {r2-r9}
73        stmia   r0!, {r2-r9}
74
75
76        /* zero the bss */
77        ldr     r1, =bsp_section_bss_end
78        ldr     r0, =bsp_section_bss_begin
79
80_bss_init:
81        mov     r2, #0
82        cmp     r0, r1
83        strlot  r2, [r0], #4
84        blo     _bss_init        /* loop while r0 < r1 */
85
86
87        /* Now we are prepared to start the BSP's C code */
88        mov     r0, #0
89#ifdef __thumb__
90        ldr     r3, =boot_card
91        bx      r3
92#else
93        bl      boot_card
94
95
96        /*
97         * Theoretically, we could return to what started us up,
98         * but we'd have to have saved the registers and stacks.
99         * Instead, we'll just reset.
100         */
101        bl      bsp_reset
102#endif
103        .code   32
104
105        /* We shouldn't get here. If we do, hang */
106_hang:  b       _hang
107
108
109/*******************************************************
110 standard exception vectors table
111 *** Must be located at address 0
112********************************************************/
113
114vector_block:
115        ldr    pc, handler_addr_reset
116        ldr    pc, handler_addr_undef
117        ldr    pc, handler_addr_swi
118        ldr    pc, handler_addr_prefetch
119        ldr    pc, handler_addr_abort
120        nop
121        ldr    pc, handler_addr_irq
122        ldr    pc, handler_addr_fiq
123
124handler_addr_reset:
125        .word  _start
126
127handler_addr_undef:
128        .word  _ARMV4_Exception_undef_default
129
130handler_addr_swi:
131        .word  _ARMV4_Exception_swi_default
132
133handler_addr_prefetch:
134        .word  _ARMV4_Exception_pref_abort_default
135
136handler_addr_abort:
137        .word  _ARMV4_Exception_data_abort_default
138
139handler_addr_reserved:
140        .word  _ARMV4_Exception_reserved_default
141
142handler_addr_irq:
143        .word  _ARMV4_Exception_interrupt
144
145handler_addr_fiq:
146        .word  _ARMV4_Exception_fiq_default
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