[8a3c70b] | 1 | /* |
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[e890774] | 2 | * Philips LPC22XX/LPC21xx Startup code |
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[8a3c70b] | 3 | * |
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[e890774] | 4 | * Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com> |
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| 5 | * Change from CSB337's code by Jay Monkman <jtm@lopingdog.com> |
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[8a3c70b] | 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[c499856] | 8 | * http://www.rtems.org/license/LICENSE. |
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[8a3c70b] | 9 | */ |
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| 10 | |
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[511dc4b] | 11 | #include <rtems/asm.h> |
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| 12 | #include <rtems/score/cpu.h> |
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[8a3c70b] | 13 | |
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| 14 | .text |
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[ac654234] | 15 | .code 32 |
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[8a3c70b] | 16 | .globl _start |
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| 17 | _start: |
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[32b8506] | 18 | /* |
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[8a3c70b] | 19 | * Since I don't plan to return to the bootloader, |
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| 20 | * I don't have to save the registers. |
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| 21 | */ |
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[32b8506] | 22 | |
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[511dc4b] | 23 | /* Set end of interrupt stack area */ |
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[ff081aee] | 24 | ldr r7, =_ISR_Stack_area_end |
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[8a3c70b] | 25 | |
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| 26 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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[511dc4b] | 27 | mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) |
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[8a3c70b] | 28 | msr cpsr, r0 |
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[f990c1a] | 29 | ldr r1, =bsp_stack_fiq_size |
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[511dc4b] | 30 | mov sp, r7 |
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| 31 | sub r7, r7, r1 |
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[8a3c70b] | 32 | |
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| 33 | /* Enter ABT mode and set up the ABT stack pointer */ |
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[511dc4b] | 34 | mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) |
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[8a3c70b] | 35 | msr cpsr, r0 |
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[f990c1a] | 36 | ldr r1, =bsp_stack_abt_size |
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[511dc4b] | 37 | mov sp, r7 |
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| 38 | sub r7, r7, r1 |
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| 39 | |
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| 40 | /* Enter UND mode and set up the UND stack pointer */ |
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| 41 | mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) |
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| 42 | msr cpsr, r0 |
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| 43 | ldr r1, =bsp_stack_und_size |
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| 44 | mov sp, r7 |
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| 45 | sub r7, r7, r1 |
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[32b8506] | 46 | |
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[511dc4b] | 47 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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| 48 | mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) |
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| 49 | msr cpsr, r0 |
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| 50 | mov sp, r7 |
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| 51 | |
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| 52 | /* |
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| 53 | * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack |
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| 54 | * (interrupts are disabled). |
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| 55 | */ |
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| 56 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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[8a3c70b] | 57 | msr cpsr, r0 |
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[511dc4b] | 58 | mov sp, r7 |
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| 59 | |
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| 60 | /* Stay in SVC mode */ |
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[32b8506] | 61 | |
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| 62 | /* |
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[8a3c70b] | 63 | * Initialize the exception vectors. This includes the |
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[32b8506] | 64 | * exceptions vectors (0x00000000-0x0000001c), and the |
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[8a3c70b] | 65 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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| 66 | */ |
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| 67 | mov r0, #0 |
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| 68 | adr r1, vector_block |
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| 69 | ldmia r1!, {r2-r9} |
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| 70 | stmia r0!, {r2-r9} |
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[32b8506] | 71 | |
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[8a3c70b] | 72 | ldmia r1!, {r2-r9} |
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| 73 | stmia r0!, {r2-r9} |
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| 74 | |
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[ac654234] | 75 | |
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| 76 | /* zero the bss */ |
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[f990c1a] | 77 | ldr r1, =bsp_section_bss_end |
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| 78 | ldr r0, =bsp_section_bss_begin |
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[ac654234] | 79 | |
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[32b8506] | 80 | _bss_init: |
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[ac654234] | 81 | mov r2, #0 |
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| 82 | cmp r0, r1 |
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| 83 | strlot r2, [r0], #4 |
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[32b8506] | 84 | blo _bss_init /* loop while r0 < r1 */ |
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[ac654234] | 85 | |
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| 86 | |
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[8a3c70b] | 87 | /* Now we are prepared to start the BSP's C code */ |
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[c187b50] | 88 | mov r0, #0 |
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| 89 | #ifdef __thumb__ |
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[ac654234] | 90 | ldr r3, =boot_card |
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| 91 | bx r3 |
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| 92 | #else |
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[8a3c70b] | 93 | bl boot_card |
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| 94 | |
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[ac654234] | 95 | |
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[32b8506] | 96 | /* |
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[8a3c70b] | 97 | * Theoretically, we could return to what started us up, |
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| 98 | * but we'd have to have saved the registers and stacks. |
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| 99 | * Instead, we'll just reset. |
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| 100 | */ |
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| 101 | bl bsp_reset |
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[ac654234] | 102 | #endif |
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| 103 | .code 32 |
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[8a3c70b] | 104 | |
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| 105 | /* We shouldn't get here. If we do, hang */ |
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| 106 | _hang: b _hang |
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| 107 | |
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| 108 | |
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| 109 | /******************************************************* |
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| 110 | standard exception vectors table |
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| 111 | *** Must be located at address 0 |
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| 112 | ********************************************************/ |
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| 113 | |
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| 114 | vector_block: |
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[2433a8ab] | 115 | ldr pc, handler_addr_reset |
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| 116 | ldr pc, handler_addr_undef |
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| 117 | ldr pc, handler_addr_swi |
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| 118 | ldr pc, handler_addr_prefetch |
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| 119 | ldr pc, handler_addr_abort |
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| 120 | nop |
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| 121 | ldr pc, handler_addr_irq |
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| 122 | ldr pc, handler_addr_fiq |
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[8a3c70b] | 123 | |
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[2433a8ab] | 124 | handler_addr_reset: |
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| 125 | .word _start |
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[8a3c70b] | 126 | |
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[2433a8ab] | 127 | handler_addr_undef: |
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| 128 | .word _ARMV4_Exception_undef_default |
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[8a3c70b] | 129 | |
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[2433a8ab] | 130 | handler_addr_swi: |
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| 131 | .word _ARMV4_Exception_swi_default |
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[32b8506] | 132 | |
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[2433a8ab] | 133 | handler_addr_prefetch: |
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| 134 | .word _ARMV4_Exception_pref_abort_default |
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[8a3c70b] | 135 | |
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[2433a8ab] | 136 | handler_addr_abort: |
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| 137 | .word _ARMV4_Exception_data_abort_default |
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[8a3c70b] | 138 | |
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[2433a8ab] | 139 | handler_addr_reserved: |
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| 140 | .word _ARMV4_Exception_reserved_default |
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| 141 | |
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| 142 | handler_addr_irq: |
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| 143 | .word _ARMV4_Exception_interrupt |
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| 144 | |
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| 145 | handler_addr_fiq: |
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| 146 | .word _ARMV4_Exception_fiq_default |
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