source: rtems/bsps/arm/rtl22xx/include/bsp/irq.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 2.8 KB
RevLine 
[a44e045b]1/*
2 * Interrupt handler Header file
3 *
[f4dc319a]4 * Copyright (c) 2010 embedded brains GmbH.
5 *
[359e537]6 * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM
7 *
[a44e045b]8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
[c499856]10 *  http://www.rtems.org/license/LICENSE.
[a44e045b]11 */
12
13#ifndef __IRQ_H__
14#define __IRQ_H__
15
16#ifndef __asm__
17
18#include <rtems.h>
[f4dc319a]19#include <rtems/irq.h>
20#include <rtems/irq-extension.h>
[c193baad]21
[f4dc319a]22#endif /* __asm__ */
[a44e045b]23
24/* possible interrupt sources on the LPC22xx */
25#define LPC22xx_INTERRUPT_WDINT  0      /* Watchdog int. 0 */
26#define LPC22xx_INTERRUPT_RSV0   1      /* Reserved int. 1 */
27#define LPC22xx_INTERRUPT_DBGRX  2      /* Embedded ICE DbgCommRx receive */
28#define LPC22xx_INTERRUPT_DBGTX  3      /* Embedded ICE DbgCommRx Transmit*/
29#define LPC22xx_INTERRUPT_TIMER0 4      /* Timer 0 */
30#define LPC22xx_INTERRUPT_TIMER1 5      /* Timer 1 */
31#define LPC22xx_INTERRUPT_UART0  6      /* UART 0 */
32#define LPC22xx_INTERRUPT_UART1  7      /* UART 1 */
33#define LPC22xx_INTERRUPT_PWM0   8      /* PWM */
34#define LPC22xx_INTERRUPT_I2C    9      /* I2C  */
35#define LPC22xx_INTERRUPT_SPI0  10      /* SPI0 */
36#define LPC22xx_INTERRUPT_SPI1  11      /* SPI1 */
37#define LPC22xx_INTERRUPT_PLL   12      /* PLL */
38#define LPC22xx_INTERRUPT_RTC   13      /* RTC */
39#define LPC22xx_INTERRUPT_EINT0 14      /* Externel Interrupt 0 */
40#define LPC22xx_INTERRUPT_EINT1 15      /* Externel Interrupt 1 */
41#define LPC22xx_INTERRUPT_EINT2 16      /* Externel Interrupt 2 */
42#define LPC22xx_INTERRUPT_EINT3 17      /* Externel Interrupt 3 */
43#define LPC22xx_INTERRUPT_ADC   18      /* AD Converter */
[c9274ae]44/* Following interrupt used by lpc229x */
[a44e045b]45#define LPC22xx_INTERRUPT_CANERR 19     /* CAN LUTerr interrupt */
46#define LPC22xx_INTERRUPT_CAN1TX 20     /* CAN1 Tx interrupt */
47#define LPC22xx_INTERRUPT_CAN1RX 21     /* CAN1 Rx interrupt */
48#define LPC22xx_INTERRUPT_CAN2TX 22     /* CAN2 Tx interrupt */
49#define LPC22xx_INTERRUPT_CAN2RX 23     /* CAN2 Rx interrupt */
50#define LPC22xx_INTERRUPT_CAN3TX 24     /* CAN1 Tx interrupt */
51#define LPC22xx_INTERRUPT_CAN3RX 25     /* CAN1 Rx interrupt */
52#define LPC22xx_INTERRUPT_CAN4TX 26     /* CAN2 Tx interrupt */
53#define LPC22xx_INTERRUPT_CAN4RX 27     /* CAN2 Rx interrupt */
54#define BSP_MAX_INT              28
55
[f4dc319a]56#define BSP_INTERRUPT_VECTOR_MIN 0
57
58#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1)
59
[359e537]60#define UNDEFINED_INSTRUCTION_VECTOR_ADDR   (*(u_long *)0x00000004L)
[a44e045b]61#define SOFTWARE_INTERRUPT_VECTOR_ADDR      (*(u_long *)0x00000008L)
62#define PREFETCH_ABORT_VECTOR_ADDR          (*(u_long *)0x0000000CL)
63#define DATA_ABORT_VECTOR_ADDR              (*(u_long *)0x00000010L)
64#define IRQ_VECTOR_ADDR                     (*(u_long *)0x00000018L)
65#define FIQ_VECTOR_ADDR                     (*(u_long *)0x0000001CL)
66
67#define DATA_ABORT_ISR_ADDR                 (*(u_long *)0x00000030L)
68#define IRQ_ISR_ADDR                        (*(u_long *)0x00000038L)
69#define FIQ_ISR_ADDR                        (*(u_long *)0x0000003CL)
70
71#endif /* __IRQ_H__ */
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