1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @ingroup raspberrypi |
---|
5 | * |
---|
6 | * @brief Raspberry pi secondary CPU and IPI HW initialization |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> |
---|
11 | * |
---|
12 | * Czech Technical University in Prague |
---|
13 | * Zikova 1903/4 |
---|
14 | * 166 36 Praha 6 |
---|
15 | * Czech Republic |
---|
16 | * |
---|
17 | * Reuses some ideas from Rohini Kulkarni <krohini1593@gmail.com> |
---|
18 | * GSoC 2015 project and Altera Cyclone-V SMP code |
---|
19 | * by embedded brains GmbH |
---|
20 | * |
---|
21 | * The license and distribution terms for this file may be |
---|
22 | * found in the file LICENSE in this distribution or at |
---|
23 | * http://www.rtems.org/license/LICENSE. |
---|
24 | */ |
---|
25 | |
---|
26 | #include <rtems/score/smpimpl.h> |
---|
27 | |
---|
28 | #include <bsp/start.h> |
---|
29 | #include <bsp/raspberrypi.h> |
---|
30 | #include <bsp.h> |
---|
31 | #include <bsp/arm-cp15-start.h> |
---|
32 | #include <libcpu/arm-cp15.h> |
---|
33 | #include <rtems.h> |
---|
34 | #include <bsp/irq-generic.h> |
---|
35 | #include <assert.h> |
---|
36 | |
---|
37 | void rpi_ipi_initialize(void) |
---|
38 | { |
---|
39 | uint32_t cpu_index_self = _SMP_Get_current_processor(); |
---|
40 | |
---|
41 | /* |
---|
42 | * Includes support only for mailbox 3 interrupt. |
---|
43 | * Further interrupt support has to be added. This will have to be integrated |
---|
44 | * with existing interrupt support for Raspberry Pi |
---|
45 | */ |
---|
46 | |
---|
47 | /* reset mailbox 3 contents to zero */ |
---|
48 | BCM2835_REG(BCM2836_MAILBOX_3_READ_CLEAR_BASE + 0x10 * cpu_index_self) = 0xffffffff; |
---|
49 | |
---|
50 | BCM2835_REG(BCM2836_MAILBOX_IRQ_CTRL(cpu_index_self)) = |
---|
51 | BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ; |
---|
52 | } |
---|
53 | |
---|
54 | void rpi_start_rtems_on_secondary_processor(void) |
---|
55 | { |
---|
56 | uint32_t ctrl; |
---|
57 | |
---|
58 | ctrl = arm_cp15_start_setup_mmu_and_cache( |
---|
59 | 0, |
---|
60 | ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z |
---|
61 | ); |
---|
62 | |
---|
63 | rpi_ipi_initialize(); |
---|
64 | |
---|
65 | arm_cp15_set_domain_access_control( |
---|
66 | ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT) |
---|
67 | ); |
---|
68 | |
---|
69 | /* FIXME: Sharing the translation table between processors is brittle */ |
---|
70 | arm_cp15_set_translation_table_base( |
---|
71 | (uint32_t *) bsp_translation_table_base |
---|
72 | ); |
---|
73 | |
---|
74 | arm_cp15_tlb_invalidate(); |
---|
75 | |
---|
76 | ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; |
---|
77 | ctrl &= ~ARM_CP15_CTRL_V; |
---|
78 | arm_cp15_set_control(ctrl); |
---|
79 | |
---|
80 | _SMP_Start_multitasking_on_secondary_processor(); |
---|
81 | } |
---|