source: rtems/bsps/arm/raspberrypi/include/bsp/raspberrypi.h @ 7632906

5
Last change on this file since 7632906 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 17.2 KB
Line 
1/**
2 * @file raspberrypi.h
3 *
4 * @ingroup raspberrypi_reg
5 *
6 * @brief Register definitions.
7 */
8
9/*
10 *  Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
11 *  Copyright (c) 2013 Alan Cudmore.
12 *  Copyright (c) 2015 Yang Qiao
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *
17 *  http://www.rtems.org/license/LICENSE
18 *
19 */
20
21#ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
22#define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
23
24#include <bspopts.h>
25#include <stdint.h>
26#include <bsp/utility.h>
27
28/**
29 * @defgroup raspberrypi_reg Register Definitions
30 *
31 * @ingroup arm_raspberrypi
32 *
33 * @brief Register Definitions
34 *
35 * @{
36 */
37
38/**
39 * @name Register Macros
40 *
41 * @{
42 */
43
44#define BCM2835_REG(x)           (*(volatile uint32_t *)(x))
45#define BCM2835_BIT(n)           (1 << (n))
46
47/** @} */
48
49/**
50 * @name Peripheral Base Register Address
51 *
52 * @{
53 */
54
55#if (BSP_IS_RPI2 == 1)
56   #define RPI_PERIPHERAL_BASE      0x3F000000
57#else
58   #define RPI_PERIPHERAL_BASE      0x20000000
59#endif
60
61#define RPI_PERIPHERAL_SIZE         0x01000000
62
63/**
64 * @name Internal ARM Timer Registers
65 *
66 * @{
67 */
68
69#define BCM2835_CLOCK_FREQ       250000000
70
71#define BCM2835_TIMER_BASE       (RPI_PERIPHERAL_BASE + 0xB400)
72
73#define BCM2835_TIMER_LOD        (BCM2835_TIMER_BASE + 0x00)
74#define BCM2835_TIMER_VAL        (BCM2835_TIMER_BASE + 0x04)
75#define BCM2835_TIMER_CTL        (BCM2835_TIMER_BASE + 0x08)
76#define BCM2835_TIMER_CLI        (BCM2835_TIMER_BASE + 0x0C)
77#define BCM2835_TIMER_RIS        (BCM2835_TIMER_BASE + 0x10)
78#define BCM2835_TIMER_MIS        (BCM2835_TIMER_BASE + 0x14)
79#define BCM2835_TIMER_RLD        (BCM2835_TIMER_BASE + 0x18)
80#define BCM2835_TIMER_DIV        (BCM2835_TIMER_BASE + 0x1C)
81#define BCM2835_TIMER_CNT        (BCM2835_TIMER_BASE + 0x20)
82
83#define BCM2835_TIMER_PRESCALE    0xF9
84
85/** @} */
86
87/**
88 * @name Power Management and Watchdog  Registers
89 *
90 * @{
91 */
92
93#define BCM2835_PM_PASSWD_MAGIC  0x5a000000
94
95#define BCM2835_PM_BASE          (RPI_PERIPHERAL_BASE + 0x100000)
96
97#define BCM2835_PM_GNRIC         (BCM2835_PM_BASE + 0x00)
98#define BCM2835_PM_GNRIC_POWUP   0x00000001
99#define BCM2835_PM_GNRIC_POWOK   0x00000002
100#define BCM2835_PM_GNRIC_ISPOW   0x00000004
101#define BCM2835_PM_GNRIC_MEMREP  0x00000008
102#define BCM2835_PM_GNRIC_MRDONE  0x00000010
103#define BCM2835_PM_GNRIC_ISFUNC  0x00000020
104#define BCM2835_PM_GNRIC_RSTN    0x00000fc0
105#define BCM2835_PM_GNRIC_ENAB    0x00001000
106#define BCM2835_PM_GNRIC_CFG     0x007f0000
107
108#define BCM2835_PM_AUDIO         (BCM2835_PM_BASE + 0x04)
109#define BCM2835_PM_AUDIO_APSM    0x000fffff
110#define BCM2835_PM_AUDIO_CTRLEN  0x00100000
111#define BCM2835_PM_AUDIO_RSTN    0x00200000
112
113#define BCM2835_PM_STATUS        (BCM2835_PM_BASE + 0x18)
114
115#define BCM2835_PM_RSTC          (BCM2835_PM_BASE + 0x1c)
116#define BCM2835_PM_RSTC_DRCFG    0x00000003
117#define BCM2835_PM_RSTC_WRCFG    0x00000030
118#define BCM2835_PM_RSTC_WRCFG_FULL   0x00000020
119#define BCM2835_PM_RSTC_SRCFG    0x00000300
120#define BCM2835_PM_RSTC_QRCFG    0x00003000
121#define BCM2835_PM_RSTC_FRCFG    0x00030000
122#define BCM2835_PM_RSTC_HRCFG    0x00300000
123
124#define BCM2835_PM_RSTS          (BCM2835_PM_BASE + 0x20)
125#define BCM2835_PM_RSTS_HADDRQ   0x00000001
126#define BCM2835_PM_RSTS_HADDRF   0x00000002
127#define BCM2835_PM_RSTS_HADDRH   0x00000004
128#define BCM2835_PM_RSTS_HADWRQ   0x00000010
129#define BCM2835_PM_RSTS_HADWRF   0x00000020
130#define BCM2835_PM_RSTS_HADWRH   0x00000040
131#define BCM2835_PM_RSTS_HADSRQ   0x00000100
132#define BCM2835_PM_RSTS_HADSRF   0x00000200
133#define BCM2835_PM_RSTS_HADSRH   0x00000400
134#define BCM2835_PM_RSTS_HADPOR   0x00001000
135
136#define BCM2835_PM_WDOG          (BCM2835_PM_BASE + 0x24)
137
138/** @} */
139
140/**
141 * @name GPIO Registers
142 *
143 * @{
144 */
145
146#define BCM2835_GPIO_REGS_BASE   (RPI_PERIPHERAL_BASE + 0x200000)
147
148#define BCM2835_GPIO_GPFSEL1     (BCM2835_GPIO_REGS_BASE + 0x04)
149#define BCM2835_GPIO_GPSET0      (BCM2835_GPIO_REGS_BASE + 0x1C)
150#define BCM2835_GPIO_GPCLR0      (BCM2835_GPIO_REGS_BASE + 0x28)
151#define BCM2835_GPIO_GPLEV0      (BCM2835_GPIO_REGS_BASE + 0x34)
152#define BCM2835_GPIO_GPEDS0      (BCM2835_GPIO_REGS_BASE + 0x40)
153#define BCM2835_GPIO_GPREN0      (BCM2835_GPIO_REGS_BASE + 0x4C)
154#define BCM2835_GPIO_GPFEN0      (BCM2835_GPIO_REGS_BASE + 0x58)
155#define BCM2835_GPIO_GPHEN0      (BCM2835_GPIO_REGS_BASE + 0x64)
156#define BCM2835_GPIO_GPLEN0      (BCM2835_GPIO_REGS_BASE + 0x70)
157#define BCM2835_GPIO_GPAREN0     (BCM2835_GPIO_REGS_BASE + 0x7C)
158#define BCM2835_GPIO_GPAFEN0     (BCM2835_GPIO_REGS_BASE + 0x88)
159#define BCM2835_GPIO_GPPUD       (BCM2835_GPIO_REGS_BASE + 0x94)
160#define BCM2835_GPIO_GPPUDCLK0   (BCM2835_GPIO_REGS_BASE + 0x98)
161
162/** @} */
163
164/**
165 * @name AUX Registers
166 *
167 * @{
168 */
169
170#define BCM2835_AUX_BASE         (RPI_PERIPHERAL_BASE + 0x215000)
171
172#define AUX_ENABLES              (BCM2835_AUX_BASE + 0x04)
173#define AUX_MU_IO_REG            (BCM2835_AUX_BASE + 0x40)
174#define AUX_MU_IER_REG           (BCM2835_AUX_BASE + 0x44)
175#define AUX_MU_IIR_REG           (BCM2835_AUX_BASE + 0x48)
176#define AUX_MU_LCR_REG           (BCM2835_AUX_BASE + 0x4C)
177#define AUX_MU_MCR_REG           (BCM2835_AUX_BASE + 0x50)
178#define AUX_MU_LSR_REG           (BCM2835_AUX_BASE + 0x54)
179#define AUX_MU_MSR_REG           (BCM2835_AUX_BASE + 0x58)
180#define AUX_MU_SCRATCH           (BCM2835_AUX_BASE + 0x5C)
181#define AUX_MU_CNTL_REG          (BCM2835_AUX_BASE + 0x60)
182#define AUX_MU_STAT_REG          (BCM2835_AUX_BASE + 0x64)
183#define AUX_MU_BAUD_REG          (BCM2835_AUX_BASE + 0x68)
184
185/** @} */
186
187/**
188 * @name UART 0 (PL011) Registers
189 *
190 * @{
191 */
192
193#define BCM2835_UART0_BASE       (RPI_PERIPHERAL_BASE + 0x201000)
194
195#define BCM2835_UART0_DR         (BCM2835_UART0_BASE + 0x00)
196#define BCM2835_UART0_RSRECR     (BCM2835_UART0_BASE + 0x04)
197#define BCM2835_UART0_FR         (BCM2835_UART0_BASE + 0x18)
198#define BCM2835_UART0_ILPR       (BCM2835_UART0_BASE + 0x20)
199#define BCM2835_UART0_IBRD       (BCM2835_UART0_BASE + 0x24)
200#define BCM2835_UART0_FBRD       (BCM2835_UART0_BASE + 0x28)
201#define BCM2835_UART0_LCRH       (BCM2835_UART0_BASE + 0x2C)
202#define BCM2835_UART0_CR         (BCM2835_UART0_BASE + 0x30)
203#define BCM2835_UART0_IFLS       (BCM2835_UART0_BASE + 0x34)
204#define BCM2835_UART0_IMSC       (BCM2835_UART0_BASE + 0x38)
205#define BCM2835_UART0_RIS        (BCM2835_UART0_BASE + 0x3C)
206#define BCM2835_UART0_MIS        (BCM2835_UART0_BASE + 0x40)
207#define BCM2835_UART0_ICR        (BCM2835_UART0_BASE + 0x44)
208#define BCM2835_UART0_DMACR      (BCM2835_UART0_BASE + 0x48)
209#define BCM2835_UART0_ITCR       (BCM2835_UART0_BASE + 0x80)
210#define BCM2835_UART0_ITIP       (BCM2835_UART0_BASE + 0x84)
211#define BCM2835_UART0_ITOP       (BCM2835_UART0_BASE + 0x88)
212#define BCM2835_UART0_TDR        (BCM2835_UART0_BASE + 0x8C)
213
214#define BCM2835_UART0_MIS_RX    0x10
215#define BCM2835_UART0_MIS_TX    0x20
216#define BCM2835_UART0_IMSC_RX   0x10
217#define BCM2835_UART0_IMSC_TX   0x20
218#define BCM2835_UART0_FR_RXFE   0x10
219#define BCM2835_UART0_FR_TXFF   0x20
220#define BCM2835_UART0_ICR_RX    0x10
221#define BCM2835_UART0_ICR_TX    0x20
222
223/** @} */
224
225/**
226 * @name I2C (BSC) Registers
227 *
228 * @{
229 */
230
231#define BCM2835_I2C_BASE           (RPI_PERIPHERAL_BASE + 0x804000)
232
233#define BCM2835_I2C_C              (BCM2835_I2C_BASE + 0x00)
234#define BCM2835_I2C_S              (BCM2835_I2C_BASE + 0x04)
235#define BCM2835_I2C_DLEN           (BCM2835_I2C_BASE + 0x08)
236#define BCM2835_I2C_A              (BCM2835_I2C_BASE + 0x0C)
237#define BCM2835_I2C_FIFO           (BCM2835_I2C_BASE + 0x10)
238#define BCM2835_I2C_DIV            (BCM2835_I2C_BASE + 0x14)
239#define BCM2835_I2C_DEL            (BCM2835_I2C_BASE + 0x18)
240#define BCM2835_I2C_CLKT           (BCM2835_I2C_BASE + 0x1C)
241
242/** @} */
243
244/**
245 * @name SPI Registers
246 *
247 * @{
248 */
249
250#define BCM2835_SPI_BASE           (RPI_PERIPHERAL_BASE + 0x204000)
251
252#define BCM2835_SPI_CS             (BCM2835_SPI_BASE + 0x00)
253#define BCM2835_SPI_FIFO           (BCM2835_SPI_BASE + 0x04)
254#define BCM2835_SPI_CLK            (BCM2835_SPI_BASE + 0x08)
255#define BCM2835_SPI_DLEN           (BCM2835_SPI_BASE + 0x0C)
256#define BCM2835_SPI_LTOH           (BCM2835_SPI_BASE + 0x10)
257#define BCM2835_SPI_DC             (BCM2835_SPI_BASE + 0x14)
258
259/** @} */
260
261/**
262 * @name I2C/SPI slave BSC Registers
263 *
264 * @{
265 */
266
267#define BCM2835_I2C_SPI_BASE       (RPI_PERIPHERAL_BASE + 0x214000)
268
269#define BCM2835_I2C_SPI_DR         (BCM2835_I2C_SPI_BASE + 0x00)
270#define BCM2835_I2C_SPI_RSR        (BCM2835_I2C_SPI_BASE + 0x04)
271#define BCM2835_I2C_SPI_SLV        (BCM2835_I2C_SPI_BASE + 0x08)
272#define BCM2835_I2C_SPI_CR         (BCM2835_I2C_SPI_BASE + 0x0C)
273#define BCM2835_I2C_SPI_FR         (BCM2835_I2C_SPI_BASE + 0x10)
274#define BCM2835_I2C_SPI_IFLS       (BCM2835_I2C_SPI_BASE + 0x14)
275#define BCM2835_I2C_SPI_IMSC       (BCM2835_I2C_SPI_BASE + 0x18)
276#define BCM2835_I2C_SPI_RIS        (BCM2835_I2C_SPI_BASE + 0x1C)
277#define BCM2835_I2C_SPI_MIS        (BCM2835_I2C_SPI_BASE + 0x20)
278#define BCM2835_I2C_SPI_ICR        (BCM2835_I2C_SPI_BASE + 0x24)
279#define BCM2835_I2C_SPI_DMACR      (BCM2835_I2C_SPI_BASE + 0x28)
280#define BCM2835_I2C_SPI_TDR        (BCM2835_I2C_SPI_BASE + 0x2C)
281#define BCM2835_I2C_SPI_GPUSTAT    (BCM2835_I2C_SPI_BASE + 0x30)
282#define BCM2835_I2C_SPI_HCTRL      (BCM2835_I2C_SPI_BASE + 0x34)
283
284/** @} */
285
286/**
287 * @name IRQ Registers
288 *
289 * @{
290 */
291
292#define BCM2835_BASE_INTC         (RPI_PERIPHERAL_BASE + 0xB200)
293
294#define BCM2835_IRQ_BASIC         (BCM2835_BASE_INTC + 0x00)
295#define BCM2835_IRQ_PENDING1      (BCM2835_BASE_INTC + 0x04)
296#define BCM2835_IRQ_PENDING2      (BCM2835_BASE_INTC + 0x08)
297#define BCM2835_IRQ_FIQ_CTRL      (BCM2835_BASE_INTC + 0x0C)
298#define BCM2835_IRQ_ENABLE1       (BCM2835_BASE_INTC + 0x10)
299#define BCM2835_IRQ_ENABLE2       (BCM2835_BASE_INTC + 0x14)
300#define BCM2835_IRQ_ENABLE_BASIC  (BCM2835_BASE_INTC + 0x18)
301#define BCM2835_IRQ_DISABLE1      (BCM2835_BASE_INTC + 0x1C)
302#define BCM2835_IRQ_DISABLE2      (BCM2835_BASE_INTC + 0x20)
303#define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24)
304
305/** @} */
306
307/**
308 * @name GPU Timer Registers
309 *
310 * @{
311 */
312
313/**
314 * NOTE: The GPU uses Compare registers 0 and 2 for
315 *       it's own RTOS. 1 and 3 are available for use in
316 *       RTEMS.
317 */
318#define BCM2835_GPU_TIMER_BASE    (RPI_PERIPHERAL_BASE + 0x3000)
319
320#define BCM2835_GPU_TIMER_CS      (BCM2835_GPU_TIMER_BASE + 0x00)
321#define BCM2835_GPU_TIMER_CS_M0   0x00000001
322#define BCM2835_GPU_TIMER_CS_M1   0x00000002
323#define BCM2835_GPU_TIMER_CS_M2   0x00000004
324#define BCM2835_GPU_TIMER_CS_M3   0x00000008
325#define BCM2835_GPU_TIMER_CLO     (BCM2835_GPU_TIMER_BASE + 0x04)
326#define BCM2835_GPU_TIMER_CHI     (BCM2835_GPU_TIMER_BASE + 0x08)
327#define BCM2835_GPU_TIMER_C0      (BCM2835_GPU_TIMER_BASE + 0x0C)
328#define BCM2835_GPU_TIMER_C1      (BCM2835_GPU_TIMER_BASE + 0x10)
329#define BCM2835_GPU_TIMER_C2      (BCM2835_GPU_TIMER_BASE + 0x14)
330#define BCM2835_GPU_TIMER_C3      (BCM2835_GPU_TIMER_BASE + 0x18)
331
332/** @} */
333
334/**
335 * @name EMMC Registers
336 *
337 * @{
338 */
339
340/**
341 * NOTE: Since the SD controller follows the SDHCI standard,
342 *       the rtems-libbsd tree already provides the remaining registers.
343 */
344
345#define BCM2835_EMMC_BASE              (RPI_PERIPHERAL_BASE + 0x300000)
346
347/** @} */
348
349/**
350* @name Mailbox Registers
351*
352* @{
353*/
354
355#define BCM2835_MBOX_BASE   (RPI_PERIPHERAL_BASE+0xB880)
356
357#define BCM2835_MBOX_PEEK   (BCM2835_MBOX_BASE+0x10)
358#define BCM2835_MBOX_READ   (BCM2835_MBOX_BASE+0x00)
359#define BCM2835_MBOX_WRITE  (BCM2835_MBOX_BASE+0x20)
360#define BCM2835_MBOX_STATUS (BCM2835_MBOX_BASE+0x18)
361#define BCM2835_MBOX_SENDER (BCM2835_MBOX_BASE+0x14)
362#define BCM2835_MBOX_CONFIG (BCM2835_MBOX_BASE+0x1C)
363
364#define BCM2835_MBOX_FULL   0x80000000
365#define BCM2835_MBOX_EMPTY  0x40000000
366
367/** @} */
368
369/**
370* @name Mailbox Channels
371*
372* @{
373*/
374
375/* Power Manager channel */
376#define BCM2835_MBOX_CHANNEL_PM         0
377/* Framebuffer channel */
378#define BCM2835_MBOX_CHANNEL_FB         1
379 /* Virtual UART channel */
380#define BCM2835_MBOX_CHANNEL_VUART      2
381 /* VCHIQ channel */
382#define BCM2835_MBOX_CHANNEL_VCHIQ      3
383 /* LEDs channel */
384#define BCM2835_MBOX_CHANNEL_LED        4
385 /* Button channel */
386#define BCM2835_MBOX_CHANNEL_BUTTON     5
387 /* Touch screen channel */
388#define BCM2835_MBOX_CHANNEL_TOUCHS     6
389/* Property tags (ARM <-> VC) channel */
390#define BCM2835_MBOX_CHANNEL_PROP_AVC   8
391 /* Property tags (VC <-> ARM) channel */
392#define BCM2835_MBOX_CHANNEL_PROP_VCA   9
393
394/** @} */
395
396/**
397* @name USB Registers
398*
399* @{
400*/
401
402#define BCM2835_USB_BASE        (RPI_PERIPHERAL_BASE + 0x980000) /* DTC_OTG USB controller */
403
404/** @} */
405
406/**
407 * @name Raspberry Pi 2 CPU Cores Local Peripherals
408 *
409 * @{
410 */
411
412#define BCM2836_CORE_LOCAL_PERIPH_BASE    0x40000000
413#define BCM2836_CORE_LOCAL_PERIPH_SIZE    0x00040000
414
415/** @} */
416
417/**
418 * @name Raspberry Pi 2 Mailbox Register Defines
419 *
420 * @{
421 */
422
423#define BCM2836_MAILBOX_0_WRITE_SET_BASE  0x40000080
424#define BCM2836_MAILBOX_1_WRITE_SET_BASE  0x40000084
425#define BCM2836_MAILBOX_2_WRITE_SET_BASE  0x40000088
426#define BCM2836_MAILBOX_3_WRITE_SET_BASE  0x4000008C
427#define BCM2836_MAILBOX_0_READ_CLEAR_BASE 0x400000C0
428#define BCM2836_MAILBOX_1_READ_CLEAR_BASE 0x400000C4
429#define BCM2836_MAILBOX_2_READ_CLEAR_BASE 0x400000C8
430#define BCM2836_MAILBOX_3_READ_CLEAR_BASE 0x400000CC
431
432/** @} */
433
434/**
435 * @name Raspberry Pi 2 Core Timer
436 *
437 * @{
438 */
439
440#define BCM2836_CORE_TIMER_CTRL           0x40000000
441
442#define BCM2836_CORE_TIMER_CTRL_APB_CLK   0x00000100
443#define BCM2836_CORE_TIMER_CTRL_INC_2     0x00000200
444
445#define BCM2836_CORE_TIMER_PRESCALER      0x40000008
446
447#define BCM2836_CORE_TIMER_LS32           0x4000001C
448#define BCM2836_CORE_TIMER_MS32           0x40000020
449
450/** @} */
451
452/**
453 * @name Raspberry Pi 2 Local Timer
454 *
455 * @{
456 */
457
458#define BCM2836_LOCAL_TIMER_CTRL          0x40000034
459
460#define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000
461#define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN   0x20000000
462#define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000
463#define BCM2836_LOCAL_TIMER_RELOAD        0x0FFFFFFF
464
465#define BCM2836_LOCAL_TIMER_IRQ_RELOAD    0x40000038
466
467#define BCM2836_LOCAL_TIMER_IRQ_CLEAR     0x80000000
468#define BCM2836_LOCAL_TIMER_RELOAD_NOW    0x40000000
469
470#define BCM2836_LOCAL_TIMER_IRQ_ROUTING   0x40000024
471#define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ       0x00
472#define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ       0x01
473#define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ       0x02
474#define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ       0x03
475#define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ       0x04
476#define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ       0x05
477#define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ       0x06
478#define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ       0x07
479
480/** @} */
481
482/**
483 * @name Raspberry Pi 2 IRQ Routing
484 *
485 * @{
486 */
487
488#define BCM2836_GPU_IRQ_ROUTING           0x4000000C
489
490#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000
491#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001
492#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002
493#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003
494
495#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000
496#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004
497#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008
498#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
499
500#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
501
502
503/** @} */
504
505/**
506 * @name Raspberry Pi 2 Interrupt Register Defines
507 *
508 * @{
509 */
510
511/* Timers interrupt control registers */
512#define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040
513#define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044
514#define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048
515#define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C
516
517#define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \
518  (BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
519
520/*
521 * Where to route timer interrupt to, IRQ/FIQ
522 * Setting both the IRQ and FIQ bit gives an FIQ
523 */
524#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ  0x01
525#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ  0x02
526#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ  0x04
527#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ  0x08
528#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ  0x10
529#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ  0x20
530#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ  0x40
531#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ  0x80
532
533/* CPU mailbox registers */
534#define BCM2836_MAILBOX_IRQ_CTRL_BASE     0x40000050
535#define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \
536  (BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx))
537/*
538 * Where to route mailbox interrupt to, IRQ/FIQ
539 * Setting both the IRQ and FIQ bit gives an FIQ
540 */
541#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ      0x01
542#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ      0x02
543#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ      0x04
544#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ      0x08
545#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ      0x10
546#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ      0x20
547#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ      0x40
548#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ      0x80
549
550#define BCM2836_IRQ_SOURCE_REG_BASE       0x40000060
551#define BCM2836_IRQ_SOURCE_REG(cpuidx) \
552  (BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
553
554#define BCM2836_FIQ_SOURCE_REG_BASE       0x40000070
555#define BCM2836_FIQ_SOURCE_REG(cpuidx) \
556  (BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
557
558#define BCM2836_IRQ_SOURCE_TIMER0         0x00000001
559#define BCM2836_IRQ_SOURCE_TIMER1         0x00000002
560#define BCM2836_IRQ_SOURCE_TIMER2         0x00000004
561#define BCM2836_IRQ_SOURCE_TIMER3         0x00000008
562#define BCM2836_IRQ_SOURCE_MBOX0          0x00000010
563#define BCM2836_IRQ_SOURCE_MBOX1          0x00000020
564#define BCM2836_IRQ_SOURCE_MBOX2          0x00000040
565#define BCM2836_IRQ_SOURCE_MBOX3          0x00000080
566#define BCM2836_IRQ_SOURCE_GPU            0x00000100
567#define BCM2836_IRQ_SOURCE_PMU            0x00000200
568#define BCM2836_IRQ_SOURCE_LOCAL_TIMER    0x00000800
569
570/** @} */
571
572#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
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