[98eb7e78] | 1 | /** |
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[feea03b6] | 2 | * @file |
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[c32b1ef] | 3 | * |
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[98eb7e78] | 4 | * @ingroup raspberrypi_reg |
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| 5 | * |
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| 6 | * @brief Register definitions. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[7aca0fe] | 10 | * Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com> |
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[61e7c69] | 11 | * Copyright (c) 2013 Alan Cudmore. |
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[33e39d31] | 12 | * Copyright (c) 2015 Yang Qiao |
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[c32b1ef] | 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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| 16 | * |
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[c499856] | 17 | * http://www.rtems.org/license/LICENSE |
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[c32b1ef] | 18 | * |
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| 19 | */ |
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| 20 | |
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| 21 | #ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H |
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| 22 | #define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H |
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| 23 | |
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[de378ad] | 24 | #include <bspopts.h> |
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[c32b1ef] | 25 | #include <stdint.h> |
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| 26 | #include <bsp/utility.h> |
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| 27 | |
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| 28 | /** |
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| 29 | * @defgroup raspberrypi_reg Register Definitions |
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| 30 | * |
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[c991eeec] | 31 | * @ingroup RTEMSBSPsARMRaspberryPi |
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[c32b1ef] | 32 | * |
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[98eb7e78] | 33 | * @brief Register Definitions |
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[c32b1ef] | 34 | * |
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| 35 | * @{ |
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| 36 | */ |
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| 37 | |
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| 38 | /** |
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| 39 | * @name Register Macros |
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| 40 | * |
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| 41 | * @{ |
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| 42 | */ |
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| 43 | |
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| 44 | #define BCM2835_REG(x) (*(volatile uint32_t *)(x)) |
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| 45 | #define BCM2835_BIT(n) (1 << (n)) |
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| 46 | |
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| 47 | /** @} */ |
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| 48 | |
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[71260b4] | 49 | /** |
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| 50 | * @name Peripheral Base Register Address |
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| 51 | * |
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| 52 | * @{ |
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| 53 | */ |
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| 54 | |
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| 55 | #if (BSP_IS_RPI2 == 1) |
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[362cf319] | 56 | #define RPI_PERIPHERAL_BASE 0x3F000000 |
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| 57 | #define BASE_OFFSET 0X3F000000 |
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[71260b4] | 58 | #else |
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[362cf319] | 59 | #define RPI_PERIPHERAL_BASE 0x20000000 |
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| 60 | #define BASE_OFFSET 0X5E000000 |
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[71260b4] | 61 | #endif |
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| 62 | |
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[362cf319] | 63 | #define RPI_PERIPHERAL_SIZE 0x01000000 |
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| 64 | |
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| 65 | /** |
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| 66 | * @name Bus to Physical address translation |
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| 67 | * Macro. |
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| 68 | * @{ |
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| 69 | */ |
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| 70 | |
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| 71 | #define BUS_TO_PHY(x) ((x) - BASE_OFFSET) |
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| 72 | |
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| 73 | /** @} */ |
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[71260b4] | 74 | |
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[c32b1ef] | 75 | /** |
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| 76 | * @name Internal ARM Timer Registers |
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| 77 | * |
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| 78 | * @{ |
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| 79 | */ |
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| 80 | |
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| 81 | #define BCM2835_CLOCK_FREQ 250000000 |
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| 82 | |
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[71260b4] | 83 | #define BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400) |
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[c32b1ef] | 84 | |
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[7aca0fe] | 85 | #define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE + 0x00) |
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| 86 | #define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE + 0x04) |
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| 87 | #define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE + 0x08) |
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| 88 | #define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE + 0x0C) |
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| 89 | #define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE + 0x10) |
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| 90 | #define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE + 0x14) |
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| 91 | #define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE + 0x18) |
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| 92 | #define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE + 0x1C) |
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| 93 | #define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE + 0x20) |
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[c32b1ef] | 94 | |
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| 95 | #define BCM2835_TIMER_PRESCALE 0xF9 |
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| 96 | |
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| 97 | /** @} */ |
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| 98 | |
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[5eb769ca] | 99 | /** |
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| 100 | * @name Power Management and Watchdog Registers |
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| 101 | * |
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| 102 | * @{ |
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| 103 | */ |
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| 104 | |
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| 105 | #define BCM2835_PM_PASSWD_MAGIC 0x5a000000 |
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| 106 | |
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| 107 | #define BCM2835_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000) |
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| 108 | |
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| 109 | #define BCM2835_PM_GNRIC (BCM2835_PM_BASE + 0x00) |
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| 110 | #define BCM2835_PM_GNRIC_POWUP 0x00000001 |
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| 111 | #define BCM2835_PM_GNRIC_POWOK 0x00000002 |
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| 112 | #define BCM2835_PM_GNRIC_ISPOW 0x00000004 |
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| 113 | #define BCM2835_PM_GNRIC_MEMREP 0x00000008 |
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| 114 | #define BCM2835_PM_GNRIC_MRDONE 0x00000010 |
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| 115 | #define BCM2835_PM_GNRIC_ISFUNC 0x00000020 |
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| 116 | #define BCM2835_PM_GNRIC_RSTN 0x00000fc0 |
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| 117 | #define BCM2835_PM_GNRIC_ENAB 0x00001000 |
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| 118 | #define BCM2835_PM_GNRIC_CFG 0x007f0000 |
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| 119 | |
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| 120 | #define BCM2835_PM_AUDIO (BCM2835_PM_BASE + 0x04) |
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| 121 | #define BCM2835_PM_AUDIO_APSM 0x000fffff |
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| 122 | #define BCM2835_PM_AUDIO_CTRLEN 0x00100000 |
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| 123 | #define BCM2835_PM_AUDIO_RSTN 0x00200000 |
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| 124 | |
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| 125 | #define BCM2835_PM_STATUS (BCM2835_PM_BASE + 0x18) |
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| 126 | |
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| 127 | #define BCM2835_PM_RSTC (BCM2835_PM_BASE + 0x1c) |
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| 128 | #define BCM2835_PM_RSTC_DRCFG 0x00000003 |
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| 129 | #define BCM2835_PM_RSTC_WRCFG 0x00000030 |
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| 130 | #define BCM2835_PM_RSTC_WRCFG_FULL 0x00000020 |
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| 131 | #define BCM2835_PM_RSTC_SRCFG 0x00000300 |
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| 132 | #define BCM2835_PM_RSTC_QRCFG 0x00003000 |
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| 133 | #define BCM2835_PM_RSTC_FRCFG 0x00030000 |
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| 134 | #define BCM2835_PM_RSTC_HRCFG 0x00300000 |
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| 135 | |
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| 136 | #define BCM2835_PM_RSTS (BCM2835_PM_BASE + 0x20) |
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| 137 | #define BCM2835_PM_RSTS_HADDRQ 0x00000001 |
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| 138 | #define BCM2835_PM_RSTS_HADDRF 0x00000002 |
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| 139 | #define BCM2835_PM_RSTS_HADDRH 0x00000004 |
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| 140 | #define BCM2835_PM_RSTS_HADWRQ 0x00000010 |
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| 141 | #define BCM2835_PM_RSTS_HADWRF 0x00000020 |
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| 142 | #define BCM2835_PM_RSTS_HADWRH 0x00000040 |
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| 143 | #define BCM2835_PM_RSTS_HADSRQ 0x00000100 |
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| 144 | #define BCM2835_PM_RSTS_HADSRF 0x00000200 |
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| 145 | #define BCM2835_PM_RSTS_HADSRH 0x00000400 |
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| 146 | #define BCM2835_PM_RSTS_HADPOR 0x00001000 |
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| 147 | |
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| 148 | #define BCM2835_PM_WDOG (BCM2835_PM_BASE + 0x24) |
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| 149 | |
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| 150 | /** @} */ |
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| 151 | |
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[c32b1ef] | 152 | /** |
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| 153 | * @name GPIO Registers |
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| 154 | * |
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| 155 | * @{ |
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| 156 | */ |
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| 157 | |
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[71260b4] | 158 | #define BCM2835_GPIO_REGS_BASE (RPI_PERIPHERAL_BASE + 0x200000) |
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[c32b1ef] | 159 | |
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[7aca0fe] | 160 | #define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE + 0x04) |
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| 161 | #define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE + 0x1C) |
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| 162 | #define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE + 0x28) |
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| 163 | #define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE + 0x34) |
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| 164 | #define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE + 0x40) |
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| 165 | #define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE + 0x4C) |
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| 166 | #define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE + 0x58) |
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| 167 | #define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE + 0x64) |
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| 168 | #define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE + 0x70) |
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| 169 | #define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE + 0x7C) |
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| 170 | #define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE + 0x88) |
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| 171 | #define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE + 0x94) |
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| 172 | #define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE + 0x98) |
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[c32b1ef] | 173 | |
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| 174 | /** @} */ |
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| 175 | |
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| 176 | /** |
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| 177 | * @name AUX Registers |
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| 178 | * |
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| 179 | * @{ |
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| 180 | */ |
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| 181 | |
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[71260b4] | 182 | #define BCM2835_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000) |
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[c32b1ef] | 183 | |
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[7aca0fe] | 184 | #define AUX_ENABLES (BCM2835_AUX_BASE + 0x04) |
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| 185 | #define AUX_MU_IO_REG (BCM2835_AUX_BASE + 0x40) |
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| 186 | #define AUX_MU_IER_REG (BCM2835_AUX_BASE + 0x44) |
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| 187 | #define AUX_MU_IIR_REG (BCM2835_AUX_BASE + 0x48) |
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| 188 | #define AUX_MU_LCR_REG (BCM2835_AUX_BASE + 0x4C) |
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| 189 | #define AUX_MU_MCR_REG (BCM2835_AUX_BASE + 0x50) |
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| 190 | #define AUX_MU_LSR_REG (BCM2835_AUX_BASE + 0x54) |
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| 191 | #define AUX_MU_MSR_REG (BCM2835_AUX_BASE + 0x58) |
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| 192 | #define AUX_MU_SCRATCH (BCM2835_AUX_BASE + 0x5C) |
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| 193 | #define AUX_MU_CNTL_REG (BCM2835_AUX_BASE + 0x60) |
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| 194 | #define AUX_MU_STAT_REG (BCM2835_AUX_BASE + 0x64) |
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| 195 | #define AUX_MU_BAUD_REG (BCM2835_AUX_BASE + 0x68) |
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[c32b1ef] | 196 | |
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| 197 | /** @} */ |
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| 198 | |
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[61e7c69] | 199 | /** @} */ |
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| 200 | |
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| 201 | /** |
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| 202 | * @name I2C (BSC) Registers |
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| 203 | * |
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| 204 | * @{ |
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| 205 | */ |
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| 206 | |
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[7aca0fe] | 207 | #define BCM2835_I2C_BASE (RPI_PERIPHERAL_BASE + 0x804000) |
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[61e7c69] | 208 | |
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[7aca0fe] | 209 | #define BCM2835_I2C_C (BCM2835_I2C_BASE + 0x00) |
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| 210 | #define BCM2835_I2C_S (BCM2835_I2C_BASE + 0x04) |
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| 211 | #define BCM2835_I2C_DLEN (BCM2835_I2C_BASE + 0x08) |
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| 212 | #define BCM2835_I2C_A (BCM2835_I2C_BASE + 0x0C) |
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| 213 | #define BCM2835_I2C_FIFO (BCM2835_I2C_BASE + 0x10) |
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| 214 | #define BCM2835_I2C_DIV (BCM2835_I2C_BASE + 0x14) |
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| 215 | #define BCM2835_I2C_DEL (BCM2835_I2C_BASE + 0x18) |
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| 216 | #define BCM2835_I2C_CLKT (BCM2835_I2C_BASE + 0x1C) |
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[c32b1ef] | 217 | |
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| 218 | /** @} */ |
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| 219 | |
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[61e7c69] | 220 | /** |
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| 221 | * @name SPI Registers |
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| 222 | * |
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| 223 | * @{ |
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| 224 | */ |
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| 225 | |
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[7aca0fe] | 226 | #define BCM2835_SPI_BASE (RPI_PERIPHERAL_BASE + 0x204000) |
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[61e7c69] | 227 | |
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[7aca0fe] | 228 | #define BCM2835_SPI_CS (BCM2835_SPI_BASE + 0x00) |
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| 229 | #define BCM2835_SPI_FIFO (BCM2835_SPI_BASE + 0x04) |
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| 230 | #define BCM2835_SPI_CLK (BCM2835_SPI_BASE + 0x08) |
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| 231 | #define BCM2835_SPI_DLEN (BCM2835_SPI_BASE + 0x0C) |
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| 232 | #define BCM2835_SPI_LTOH (BCM2835_SPI_BASE + 0x10) |
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| 233 | #define BCM2835_SPI_DC (BCM2835_SPI_BASE + 0x14) |
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[61e7c69] | 234 | |
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| 235 | /** @} */ |
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| 236 | |
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| 237 | /** |
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| 238 | * @name I2C/SPI slave BSC Registers |
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| 239 | * |
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| 240 | * @{ |
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| 241 | */ |
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| 242 | |
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[7aca0fe] | 243 | #define BCM2835_I2C_SPI_BASE (RPI_PERIPHERAL_BASE + 0x214000) |
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| 244 | |
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| 245 | #define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE + 0x00) |
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| 246 | #define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE + 0x04) |
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| 247 | #define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE + 0x08) |
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| 248 | #define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE + 0x0C) |
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| 249 | #define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE + 0x10) |
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| 250 | #define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE + 0x14) |
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| 251 | #define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE + 0x18) |
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| 252 | #define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE + 0x1C) |
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| 253 | #define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE + 0x20) |
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| 254 | #define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE + 0x24) |
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| 255 | #define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE + 0x28) |
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| 256 | #define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE + 0x2C) |
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| 257 | #define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE + 0x30) |
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| 258 | #define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE + 0x34) |
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[61e7c69] | 259 | |
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| 260 | /** @} */ |
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[c32b1ef] | 261 | |
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| 262 | /** |
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| 263 | * @name IRQ Registers |
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| 264 | * |
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| 265 | * @{ |
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| 266 | */ |
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| 267 | |
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[71260b4] | 268 | #define BCM2835_BASE_INTC (RPI_PERIPHERAL_BASE + 0xB200) |
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[c32b1ef] | 269 | |
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| 270 | #define BCM2835_IRQ_BASIC (BCM2835_BASE_INTC + 0x00) |
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| 271 | #define BCM2835_IRQ_PENDING1 (BCM2835_BASE_INTC + 0x04) |
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| 272 | #define BCM2835_IRQ_PENDING2 (BCM2835_BASE_INTC + 0x08) |
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| 273 | #define BCM2835_IRQ_FIQ_CTRL (BCM2835_BASE_INTC + 0x0C) |
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| 274 | #define BCM2835_IRQ_ENABLE1 (BCM2835_BASE_INTC + 0x10) |
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| 275 | #define BCM2835_IRQ_ENABLE2 (BCM2835_BASE_INTC + 0x14) |
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| 276 | #define BCM2835_IRQ_ENABLE_BASIC (BCM2835_BASE_INTC + 0x18) |
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| 277 | #define BCM2835_IRQ_DISABLE1 (BCM2835_BASE_INTC + 0x1C) |
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| 278 | #define BCM2835_IRQ_DISABLE2 (BCM2835_BASE_INTC + 0x20) |
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| 279 | #define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24) |
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| 280 | |
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| 281 | /** @} */ |
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| 282 | |
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| 283 | /** |
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| 284 | * @name GPU Timer Registers |
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| 285 | * |
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| 286 | * @{ |
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| 287 | */ |
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| 288 | |
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| 289 | /** |
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| 290 | * NOTE: The GPU uses Compare registers 0 and 2 for |
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| 291 | * it's own RTOS. 1 and 3 are available for use in |
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| 292 | * RTEMS. |
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| 293 | */ |
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[71260b4] | 294 | #define BCM2835_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000) |
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[c32b1ef] | 295 | |
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[40f49d1] | 296 | #define BCM2835_GPU_TIMER_CS (BCM2835_GPU_TIMER_BASE + 0x00) |
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| 297 | #define BCM2835_GPU_TIMER_CS_M0 0x00000001 |
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| 298 | #define BCM2835_GPU_TIMER_CS_M1 0x00000002 |
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| 299 | #define BCM2835_GPU_TIMER_CS_M2 0x00000004 |
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| 300 | #define BCM2835_GPU_TIMER_CS_M3 0x00000008 |
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| 301 | #define BCM2835_GPU_TIMER_CLO (BCM2835_GPU_TIMER_BASE + 0x04) |
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| 302 | #define BCM2835_GPU_TIMER_CHI (BCM2835_GPU_TIMER_BASE + 0x08) |
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| 303 | #define BCM2835_GPU_TIMER_C0 (BCM2835_GPU_TIMER_BASE + 0x0C) |
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| 304 | #define BCM2835_GPU_TIMER_C1 (BCM2835_GPU_TIMER_BASE + 0x10) |
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| 305 | #define BCM2835_GPU_TIMER_C2 (BCM2835_GPU_TIMER_BASE + 0x14) |
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| 306 | #define BCM2835_GPU_TIMER_C3 (BCM2835_GPU_TIMER_BASE + 0x18) |
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[7aca0fe] | 307 | |
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| 308 | /** @} */ |
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| 309 | |
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| 310 | /** |
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| 311 | * @name EMMC Registers |
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| 312 | * |
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| 313 | * @{ |
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| 314 | */ |
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| 315 | |
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| 316 | /** |
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| 317 | * NOTE: Since the SD controller follows the SDHCI standard, |
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| 318 | * the rtems-libbsd tree already provides the remaining registers. |
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| 319 | */ |
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| 320 | |
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| 321 | #define BCM2835_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000) |
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[c32b1ef] | 322 | |
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| 323 | /** @} */ |
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| 324 | |
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[33e39d31] | 325 | /** |
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| 326 | * @name Mailbox Registers |
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| 327 | * |
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| 328 | * @{ |
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| 329 | */ |
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| 330 | |
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| 331 | #define BCM2835_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880) |
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| 332 | |
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| 333 | #define BCM2835_MBOX_PEEK (BCM2835_MBOX_BASE+0x10) |
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| 334 | #define BCM2835_MBOX_READ (BCM2835_MBOX_BASE+0x00) |
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| 335 | #define BCM2835_MBOX_WRITE (BCM2835_MBOX_BASE+0x20) |
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| 336 | #define BCM2835_MBOX_STATUS (BCM2835_MBOX_BASE+0x18) |
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| 337 | #define BCM2835_MBOX_SENDER (BCM2835_MBOX_BASE+0x14) |
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| 338 | #define BCM2835_MBOX_CONFIG (BCM2835_MBOX_BASE+0x1C) |
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| 339 | |
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| 340 | #define BCM2835_MBOX_FULL 0x80000000 |
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| 341 | #define BCM2835_MBOX_EMPTY 0x40000000 |
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| 342 | |
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| 343 | /** @} */ |
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| 344 | |
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| 345 | /** |
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| 346 | * @name Mailbox Channels |
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| 347 | * |
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| 348 | * @{ |
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| 349 | */ |
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| 350 | |
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| 351 | /* Power Manager channel */ |
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| 352 | #define BCM2835_MBOX_CHANNEL_PM 0 |
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| 353 | /* Framebuffer channel */ |
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| 354 | #define BCM2835_MBOX_CHANNEL_FB 1 |
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| 355 | /* Virtual UART channel */ |
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| 356 | #define BCM2835_MBOX_CHANNEL_VUART 2 |
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| 357 | /* VCHIQ channel */ |
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| 358 | #define BCM2835_MBOX_CHANNEL_VCHIQ 3 |
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| 359 | /* LEDs channel */ |
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| 360 | #define BCM2835_MBOX_CHANNEL_LED 4 |
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| 361 | /* Button channel */ |
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| 362 | #define BCM2835_MBOX_CHANNEL_BUTTON 5 |
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| 363 | /* Touch screen channel */ |
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| 364 | #define BCM2835_MBOX_CHANNEL_TOUCHS 6 |
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| 365 | /* Property tags (ARM <-> VC) channel */ |
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| 366 | #define BCM2835_MBOX_CHANNEL_PROP_AVC 8 |
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| 367 | /* Property tags (VC <-> ARM) channel */ |
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| 368 | #define BCM2835_MBOX_CHANNEL_PROP_VCA 9 |
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| 369 | |
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| 370 | /** @} */ |
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| 371 | |
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[1c62f7ee] | 372 | /** |
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| 373 | * @name USB Registers |
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| 374 | * |
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| 375 | * @{ |
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| 376 | */ |
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| 377 | |
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| 378 | #define BCM2835_USB_BASE (RPI_PERIPHERAL_BASE + 0x980000) /* DTC_OTG USB controller */ |
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| 379 | |
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| 380 | /** @} */ |
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[33e39d31] | 381 | |
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[4c53be1] | 382 | /** |
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| 383 | * @name Raspberry Pi 2 CPU Cores Local Peripherals |
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| 384 | * |
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| 385 | * @{ |
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| 386 | */ |
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| 387 | |
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| 388 | #define BCM2836_CORE_LOCAL_PERIPH_BASE 0x40000000 |
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| 389 | #define BCM2836_CORE_LOCAL_PERIPH_SIZE 0x00040000 |
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| 390 | |
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| 391 | /** @} */ |
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| 392 | |
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[bf62c39] | 393 | /** |
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| 394 | * @name Raspberry Pi 2 Mailbox Register Defines |
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| 395 | * |
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| 396 | * @{ |
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| 397 | */ |
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| 398 | |
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| 399 | #define BCM2836_MAILBOX_0_WRITE_SET_BASE 0x40000080 |
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| 400 | #define BCM2836_MAILBOX_1_WRITE_SET_BASE 0x40000084 |
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| 401 | #define BCM2836_MAILBOX_2_WRITE_SET_BASE 0x40000088 |
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| 402 | #define BCM2836_MAILBOX_3_WRITE_SET_BASE 0x4000008C |
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| 403 | #define BCM2836_MAILBOX_0_READ_CLEAR_BASE 0x400000C0 |
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| 404 | #define BCM2836_MAILBOX_1_READ_CLEAR_BASE 0x400000C4 |
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| 405 | #define BCM2836_MAILBOX_2_READ_CLEAR_BASE 0x400000C8 |
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| 406 | #define BCM2836_MAILBOX_3_READ_CLEAR_BASE 0x400000CC |
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| 407 | |
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[4c53be1] | 408 | /** @} */ |
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| 409 | |
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| 410 | /** |
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| 411 | * @name Raspberry Pi 2 Core Timer |
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| 412 | * |
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| 413 | * @{ |
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| 414 | */ |
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| 415 | |
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| 416 | #define BCM2836_CORE_TIMER_CTRL 0x40000000 |
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| 417 | |
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| 418 | #define BCM2836_CORE_TIMER_CTRL_APB_CLK 0x00000100 |
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| 419 | #define BCM2836_CORE_TIMER_CTRL_INC_2 0x00000200 |
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| 420 | |
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| 421 | #define BCM2836_CORE_TIMER_PRESCALER 0x40000008 |
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| 422 | |
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| 423 | #define BCM2836_CORE_TIMER_LS32 0x4000001C |
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| 424 | #define BCM2836_CORE_TIMER_MS32 0x40000020 |
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| 425 | |
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| 426 | /** @} */ |
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| 427 | |
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| 428 | /** |
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| 429 | * @name Raspberry Pi 2 Local Timer |
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| 430 | * |
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| 431 | * @{ |
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| 432 | */ |
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| 433 | |
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| 434 | #define BCM2836_LOCAL_TIMER_CTRL 0x40000034 |
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| 435 | |
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| 436 | #define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000 |
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| 437 | #define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN 0x20000000 |
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| 438 | #define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000 |
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| 439 | #define BCM2836_LOCAL_TIMER_RELOAD 0x0FFFFFFF |
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| 440 | |
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| 441 | #define BCM2836_LOCAL_TIMER_IRQ_RELOAD 0x40000038 |
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| 442 | |
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| 443 | #define BCM2836_LOCAL_TIMER_IRQ_CLEAR 0x80000000 |
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| 444 | #define BCM2836_LOCAL_TIMER_RELOAD_NOW 0x40000000 |
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| 445 | |
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| 446 | #define BCM2836_LOCAL_TIMER_IRQ_ROUTING 0x40000024 |
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| 447 | #define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ 0x00 |
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| 448 | #define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ 0x01 |
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| 449 | #define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ 0x02 |
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| 450 | #define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ 0x03 |
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| 451 | #define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ 0x04 |
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| 452 | #define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ 0x05 |
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| 453 | #define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ 0x06 |
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| 454 | #define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ 0x07 |
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| 455 | |
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| 456 | /** @} */ |
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| 457 | |
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| 458 | /** |
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| 459 | * @name Raspberry Pi 2 IRQ Routing |
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| 460 | * |
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| 461 | * @{ |
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| 462 | */ |
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| 463 | |
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| 464 | #define BCM2836_GPU_IRQ_ROUTING 0x4000000C |
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| 465 | |
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| 466 | #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000 |
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| 467 | #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001 |
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| 468 | #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002 |
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| 469 | #define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003 |
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| 470 | |
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| 471 | #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000 |
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| 472 | #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004 |
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| 473 | #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008 |
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| 474 | #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C |
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| 475 | |
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| 476 | #define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C |
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| 477 | |
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| 478 | |
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[bf62c39] | 479 | /** @} */ |
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| 480 | |
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| 481 | /** |
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| 482 | * @name Raspberry Pi 2 Interrupt Register Defines |
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| 483 | * |
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| 484 | * @{ |
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| 485 | */ |
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| 486 | |
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[4c53be1] | 487 | /* Timers interrupt control registers */ |
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| 488 | #define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040 |
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| 489 | #define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044 |
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| 490 | #define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048 |
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| 491 | #define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C |
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| 492 | |
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| 493 | #define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \ |
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| 494 | (BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx)) |
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| 495 | |
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| 496 | /* |
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| 497 | * Where to route timer interrupt to, IRQ/FIQ |
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| 498 | * Setting both the IRQ and FIQ bit gives an FIQ |
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| 499 | */ |
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| 500 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ 0x01 |
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| 501 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ 0x02 |
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| 502 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ 0x04 |
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| 503 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ 0x08 |
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| 504 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ 0x10 |
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| 505 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ 0x20 |
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| 506 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ 0x40 |
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| 507 | #define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ 0x80 |
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| 508 | |
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| 509 | /* CPU mailbox registers */ |
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| 510 | #define BCM2836_MAILBOX_IRQ_CTRL_BASE 0x40000050 |
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| 511 | #define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \ |
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| 512 | (BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx)) |
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| 513 | /* |
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| 514 | * Where to route mailbox interrupt to, IRQ/FIQ |
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| 515 | * Setting both the IRQ and FIQ bit gives an FIQ |
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| 516 | */ |
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| 517 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ 0x01 |
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| 518 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ 0x02 |
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| 519 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ 0x04 |
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| 520 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ 0x08 |
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| 521 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ 0x10 |
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| 522 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ 0x20 |
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| 523 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ 0x40 |
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| 524 | #define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ 0x80 |
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| 525 | |
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| 526 | #define BCM2836_IRQ_SOURCE_REG_BASE 0x40000060 |
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| 527 | #define BCM2836_IRQ_SOURCE_REG(cpuidx) \ |
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| 528 | (BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx)) |
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| 529 | |
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| 530 | #define BCM2836_FIQ_SOURCE_REG_BASE 0x40000070 |
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| 531 | #define BCM2836_FIQ_SOURCE_REG(cpuidx) \ |
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| 532 | (BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx)) |
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| 533 | |
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| 534 | #define BCM2836_IRQ_SOURCE_TIMER0 0x00000001 |
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| 535 | #define BCM2836_IRQ_SOURCE_TIMER1 0x00000002 |
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| 536 | #define BCM2836_IRQ_SOURCE_TIMER2 0x00000004 |
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| 537 | #define BCM2836_IRQ_SOURCE_TIMER3 0x00000008 |
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| 538 | #define BCM2836_IRQ_SOURCE_MBOX0 0x00000010 |
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| 539 | #define BCM2836_IRQ_SOURCE_MBOX1 0x00000020 |
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| 540 | #define BCM2836_IRQ_SOURCE_MBOX2 0x00000040 |
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| 541 | #define BCM2836_IRQ_SOURCE_MBOX3 0x00000080 |
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| 542 | #define BCM2836_IRQ_SOURCE_GPU 0x00000100 |
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| 543 | #define BCM2836_IRQ_SOURCE_PMU 0x00000200 |
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| 544 | #define BCM2836_IRQ_SOURCE_LOCAL_TIMER 0x00000800 |
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[bf62c39] | 545 | |
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[c32b1ef] | 546 | /** @} */ |
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| 547 | |
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| 548 | #endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */ |
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