1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup lpc32xx_emc |
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7 | * |
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8 | * @brief EMC support implementation. |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (c) 2010 embedded brains GmbH & Co. KG |
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13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
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15 | * modification, are permitted provided that the following conditions |
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16 | * are met: |
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17 | * 1. Redistributions of source code must retain the above copyright |
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18 | * notice, this list of conditions and the following disclaimer. |
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19 | * 2. Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the distribution. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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27 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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33 | * POSSIBILITY OF SUCH DAMAGE. |
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34 | */ |
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35 | |
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36 | #include <bsp/emc.h> |
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37 | |
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38 | #include <bsp.h> |
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39 | #include <bsp/mmu.h> |
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40 | |
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41 | static volatile lpc_emc *const emc = &lpc32xx.emc; |
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42 | |
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43 | static volatile lpc32xx_emc_ahb *const emc_ahb = &lpc32xx.emc_ahb [0]; |
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44 | |
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45 | static void dynamic_init(const lpc32xx_emc_dynamic_config *cfg) |
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46 | { |
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47 | uint32_t chip_begin = LPC32XX_BASE_EMC_DYCS_0; |
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48 | uint32_t dynamiccontrol = (cfg->control | EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS) |
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49 | & ~EMC_DYN_CTRL_I_MASK; |
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50 | size_t i = 0; |
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51 | |
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52 | LPC32XX_SDRAMCLK_CTRL = cfg->sdramclk_ctrl; |
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53 | |
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54 | emc->dynamicreadconfig = cfg->readconfig; |
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55 | |
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56 | /* Timings */ |
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57 | emc->dynamictrp = cfg->trp; |
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58 | emc->dynamictras = cfg->tras; |
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59 | emc->dynamictsrex = cfg->tsrex; |
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60 | emc->dynamictwr = cfg->twr; |
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61 | emc->dynamictrc = cfg->trc; |
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62 | emc->dynamictrfc = cfg->trfc; |
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63 | emc->dynamictxsr = cfg->txsr; |
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64 | emc->dynamictrrd = cfg->trrd; |
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65 | emc->dynamictmrd = cfg->tmrd; |
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66 | emc->dynamictcdlr = cfg->tcdlr; |
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67 | for (i = 0; i < EMC_DYN_CHIP_COUNT; ++i) { |
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68 | if (cfg->chip [i].size != 0) { |
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69 | emc->dynamic [i].config = cfg->chip [i].config; |
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70 | emc->dynamic [i].rascas = cfg->chip [i].rascas; |
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71 | } |
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72 | } |
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73 | |
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74 | /* NOP period */ |
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75 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_NOP; |
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76 | lpc32xx_micro_seconds_delay(cfg->nop_time_in_us); |
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77 | |
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78 | /* Precharge */ |
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79 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_PALL; |
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80 | emc->dynamicrefresh = 1; |
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81 | /* FIXME: Why a delay, why this value? */ |
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82 | lpc32xx_micro_seconds_delay(10); |
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83 | |
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84 | /* Refresh timing */ |
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85 | emc->dynamicrefresh = cfg->refresh; |
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86 | /* FIXME: Why a delay, why this value? */ |
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87 | lpc32xx_micro_seconds_delay(16); |
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88 | |
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89 | /* Set modes */ |
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90 | for (i = 0; i < EMC_DYN_CHIP_COUNT; ++i) { |
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91 | if (cfg->chip [i].size != 0) { |
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92 | lpc32xx_set_translation_table_entries( |
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93 | (void *) chip_begin, |
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94 | (void *) (chip_begin + cfg->chip [i].size), |
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95 | LPC32XX_MMU_READ_WRITE |
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96 | ); |
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97 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE; |
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98 | *(volatile uint32_t *)(chip_begin + cfg->chip [i].mode); |
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99 | emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE; |
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100 | *(volatile uint32_t *)(chip_begin + cfg->chip [i].extmode); |
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101 | } |
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102 | chip_begin += 0x20000000; |
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103 | } |
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104 | |
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105 | emc->dynamiccontrol = cfg->control; |
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106 | } |
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107 | |
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108 | void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg) |
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109 | { |
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110 | /* Enable buffers in AHB ports */ |
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111 | emc_ahb [0].control = EMC_AHB_PORT_BUFF_EN; |
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112 | emc_ahb [3].control = EMC_AHB_PORT_BUFF_EN; |
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113 | emc_ahb [4].control = EMC_AHB_PORT_BUFF_EN; |
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114 | |
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115 | /* Set AHB port timeouts */ |
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116 | emc_ahb [0].timeout = EMC_AHB_TIMEOUT(32); |
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117 | emc_ahb [3].timeout = EMC_AHB_TIMEOUT(32); |
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118 | emc_ahb [4].timeout = EMC_AHB_TIMEOUT(32); |
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119 | |
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120 | /* Enable EMC */ |
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121 | emc->control = EMC_CTRL_E, |
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122 | emc->config = 0; |
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123 | |
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124 | dynamic_init(dyn_cfg); |
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125 | } |
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