1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx_i2c |
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5 | * |
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6 | * @brief I2C support API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.org/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #ifndef LIBBSP_ARM_LPC32XX_I2C_H |
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23 | #define LIBBSP_ARM_LPC32XX_I2C_H |
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24 | |
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25 | #include <rtems.h> |
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26 | |
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27 | #include <bsp/lpc32xx.h> |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif /* __cplusplus */ |
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32 | |
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33 | /** |
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34 | * @defgroup lpc32xx_i2c I2C Support |
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35 | * |
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36 | * @ingroup RTEMSBSPsARMLPC32XX |
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37 | * |
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38 | * @brief I2C Support |
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39 | * |
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40 | * All writes and reads will be performed in master mode. Exclusive bus access |
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41 | * will be assumed. |
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42 | * |
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43 | * @{ |
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44 | */ |
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45 | |
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46 | /** |
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47 | * @name I2C Clock Control Register (I2CCLK_CTRL) |
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48 | * |
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49 | * @{ |
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50 | */ |
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51 | |
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52 | #define I2CCLK_1_EN BSP_BIT32(0) |
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53 | #define I2CCLK_2_EN BSP_BIT32(1) |
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54 | #define I2CCLK_1_HIGH_DRIVE BSP_BIT32(2) |
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55 | #define I2CCLK_2_HIGH_DRIVE BSP_BIT32(3) |
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56 | #define I2CCLK_USB_HIGH_DRIVE BSP_BIT32(4) |
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57 | |
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58 | /** @} */ |
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59 | |
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60 | /** |
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61 | * @name I2C TX Data FIFO Register (I2Cn_TX) |
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62 | * |
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63 | * @{ |
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64 | */ |
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65 | |
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66 | #define I2C_TX_READ BSP_BIT32(0) |
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67 | #define I2C_TX_ADDR(val) BSP_FLD32(val, 1, 7) |
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68 | #define I2C_TX_START BSP_BIT32(8) |
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69 | #define I2C_TX_STOP BSP_BIT32(9) |
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70 | |
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71 | /** @} */ |
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72 | |
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73 | /** |
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74 | * @name I2C Status Register (I2Cn_STAT) |
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75 | * |
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76 | * @{ |
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77 | */ |
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78 | |
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79 | #define I2C_STAT_TDI BSP_BIT32(0) |
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80 | #define I2C_STAT_AFI BSP_BIT32(1) |
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81 | #define I2C_STAT_NAI BSP_BIT32(2) |
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82 | #define I2C_STAT_DRMI BSP_BIT32(3) |
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83 | #define I2C_STAT_DRSI BSP_BIT32(4) |
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84 | #define I2C_STAT_ACTIVE BSP_BIT32(5) |
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85 | #define I2C_STAT_SCL BSP_BIT32(6) |
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86 | #define I2C_STAT_SDA BSP_BIT32(7) |
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87 | #define I2C_STAT_RFF BSP_BIT32(8) |
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88 | #define I2C_STAT_RFE BSP_BIT32(9) |
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89 | #define I2C_STAT_TFF BSP_BIT32(10) |
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90 | #define I2C_STAT_TFE BSP_BIT32(11) |
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91 | #define I2C_STAT_TFFS BSP_BIT32(12) |
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92 | #define I2C_STAT_TFES BSP_BIT32(13) |
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93 | |
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94 | /** @} */ |
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95 | |
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96 | /** |
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97 | * @name I2C Control Register (I2Cn_CTRL) |
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98 | * |
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99 | * @{ |
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100 | */ |
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101 | |
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102 | #define I2C_CTRL_TDIE BSP_BIT32(0) |
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103 | #define I2C_CTRL_AFIE BSP_BIT32(1) |
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104 | #define I2C_CTRL_NAIE BSP_BIT32(2) |
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105 | #define I2C_CTRL_DRMIE BSP_BIT32(3) |
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106 | #define I2C_CTRL_DRSIE BSP_BIT32(4) |
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107 | #define I2C_CTRL_RFFIE BSP_BIT32(5) |
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108 | #define I2C_CTRL_RFDAIE BSP_BIT32(6) |
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109 | #define I2C_CTRL_TFFIO BSP_BIT32(7) |
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110 | #define I2C_CTRL_RESET BSP_BIT32(8) |
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111 | #define I2C_CTRL_SEVEN BSP_BIT32(9) |
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112 | #define I2C_CTRL_TFFSIE BSP_BIT32(10) |
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113 | |
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114 | /** @} */ |
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115 | |
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116 | /** |
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117 | * @brief Initializes the I2C module @a i2c. |
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118 | * |
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119 | * Valid @a clock_in_hz values are 100000 and 400000. |
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120 | * |
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121 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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122 | * @retval RTEMS_INVALID_ID Invalid @a i2c value. |
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123 | * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. |
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124 | */ |
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125 | rtems_status_code lpc32xx_i2c_init( |
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126 | volatile lpc32xx_i2c *i2c, |
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127 | unsigned clock_in_hz |
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128 | ); |
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129 | |
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130 | /** |
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131 | * @brief Resets the I2C module @a i2c. |
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132 | */ |
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133 | void lpc32xx_i2c_reset(volatile lpc32xx_i2c *i2c); |
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134 | |
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135 | /** |
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136 | * @brief Sets the I2C module @a i2c clock. |
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137 | * |
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138 | * Valid @a clock_in_hz values are 100000 and 400000. |
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139 | * |
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140 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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141 | * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. |
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142 | */ |
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143 | rtems_status_code lpc32xx_i2c_clock( |
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144 | volatile lpc32xx_i2c *i2c, |
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145 | unsigned clock_in_hz |
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146 | ); |
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147 | |
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148 | /** |
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149 | * @brief Starts a write transaction on the I2C module @a i2c. |
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150 | * |
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151 | * The address parameter @a addr must not contain the read/write bit. |
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152 | * |
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153 | * The error status may be delayed to the next |
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154 | * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. |
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155 | * |
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156 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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157 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
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158 | */ |
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159 | rtems_status_code lpc32xx_i2c_write_start( |
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160 | volatile lpc32xx_i2c *i2c, |
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161 | unsigned addr |
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162 | ); |
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163 | |
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164 | /** |
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165 | * @brief Writes data via the I2C module @a i2c with optional stop. |
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166 | * |
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167 | * The error status may be delayed to the next |
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168 | * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. |
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169 | * |
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170 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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171 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
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172 | */ |
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173 | rtems_status_code lpc32xx_i2c_write_with_optional_stop( |
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174 | volatile lpc32xx_i2c *i2c, |
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175 | const uint8_t *out, |
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176 | size_t n, |
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177 | bool stop |
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178 | ); |
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179 | |
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180 | /** |
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181 | * @brief Starts a read transaction on the I2C module @a i2c. |
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182 | * |
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183 | * The address parameter @a addr must not contain the read/write bit. |
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184 | * |
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185 | * The error status may be delayed to the next |
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186 | * lpc32xx_i2c_read_with_optional_stop() due to controller flaws. |
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187 | * |
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188 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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189 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
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190 | */ |
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191 | rtems_status_code lpc32xx_i2c_read_start( |
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192 | volatile lpc32xx_i2c *i2c, |
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193 | unsigned addr |
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194 | ); |
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195 | |
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196 | /** |
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197 | * @brief Reads data via the I2C module @a i2c with optional stop. |
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198 | * |
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199 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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200 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
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201 | * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false. |
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202 | */ |
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203 | rtems_status_code lpc32xx_i2c_read_with_optional_stop( |
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204 | volatile lpc32xx_i2c *i2c, |
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205 | uint8_t *in, |
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206 | size_t n, |
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207 | bool stop |
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208 | ); |
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209 | |
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210 | /** |
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211 | * @brief Writes and reads data via the I2C module @a i2c. |
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212 | * |
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213 | * This will be one bus transaction. |
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214 | * |
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215 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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216 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
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217 | */ |
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218 | rtems_status_code lpc32xx_i2c_write_and_read( |
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219 | volatile lpc32xx_i2c *i2c, |
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220 | unsigned addr, |
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221 | const uint8_t *out, |
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222 | size_t out_size, |
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223 | uint8_t *in, |
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224 | size_t in_size |
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225 | ); |
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226 | |
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227 | /** |
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228 | * @brief Writes data via the I2C module @a i2c. |
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229 | * |
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230 | * This will be one bus transaction. |
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231 | * |
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232 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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233 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
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234 | */ |
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235 | static inline rtems_status_code lpc32xx_i2c_write( |
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236 | volatile lpc32xx_i2c *i2c, |
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237 | unsigned addr, |
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238 | const uint8_t *out, |
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239 | size_t out_size |
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240 | ) |
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241 | { |
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242 | return lpc32xx_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0); |
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243 | } |
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244 | |
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245 | /** |
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246 | * @brief Reads data via the I2C module @a i2c. |
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247 | * |
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248 | * This will be one bus transaction. |
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249 | * |
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250 | * @retval RTEMS_SUCCESSFUL Successful operation. |
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251 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
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252 | */ |
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253 | static inline rtems_status_code lpc32xx_i2c_read( |
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254 | volatile lpc32xx_i2c *i2c, |
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255 | unsigned addr, |
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256 | uint8_t *in, |
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257 | size_t in_size |
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258 | ) |
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259 | { |
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260 | return lpc32xx_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size); |
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261 | } |
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262 | |
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263 | /** @} */ |
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264 | |
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265 | #ifdef __cplusplus |
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266 | } |
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267 | #endif /* __cplusplus */ |
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268 | |
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269 | #endif /* LIBBSP_ARM_LPC32XX_I2C_H */ |
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