1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc32xx_emc |
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5 | * |
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6 | * @brief EMC support API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_LPC32XX_EMC_H |
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24 | #define LIBBSP_ARM_LPC32XX_EMC_H |
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25 | |
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26 | #include <rtems.h> |
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27 | |
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28 | #include <bsp/lpc-emc.h> |
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29 | |
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30 | #ifdef __cplusplus |
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31 | extern "C" { |
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32 | #endif /* __cplusplus */ |
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33 | |
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34 | /** |
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35 | * @addtogroup lpc_emc |
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36 | * |
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37 | * @brief EMC Support |
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38 | * |
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39 | * @{ |
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40 | */ |
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41 | |
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42 | /** |
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43 | * @name SDRAM Clock Control Register (SDRAMCLK_CTRL) |
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44 | * |
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45 | * @{ |
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46 | */ |
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47 | |
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48 | #define SDRAMCLK_CLOCKS_DIS BSP_BIT32(0) |
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49 | #define SDRAMCLK_DDR_MODE BSP_BIT32(1) |
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50 | #define SDRAMCLK_DDR_DQSIN_DELAY(val) BSP_FLD32(val, 2, 6) |
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51 | #define SDRAMCLK_RTC_TICK_EN BSP_BIT32(7) |
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52 | #define SDRAMCLK_SW_DDR_CAL BSP_BIT32(8) |
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53 | #define SDRAMCLK_CAL_DELAY BSP_BIT32(9) |
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54 | #define SDRAMCLK_SENSITIVITY_FACTOR(val) BSP_FLD32(val, 10, 12) |
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55 | #define SDRAMCLK_DCA_STATUS BSP_BIT32(13) |
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56 | #define SDRAMCLK_COMMAND_DELAY(val) BSP_FLD32(val, 14, 18) |
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57 | #define SDRAMCLK_SW_DDR_RESET BSP_BIT32(19) |
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58 | #define SDRAMCLK_PIN_1_FAST BSP_BIT32(20) |
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59 | #define SDRAMCLK_PIN_2_FAST BSP_BIT32(21) |
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60 | #define SDRAMCLK_PIN_3_FAST BSP_BIT32(22) |
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61 | |
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62 | /** @} */ |
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63 | |
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64 | /** |
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65 | * @name EMC AHB Control Register (EMCAHBControl) |
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66 | * |
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67 | * @{ |
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68 | */ |
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69 | |
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70 | #define EMC_AHB_PORT_BUFF_EN BSP_BIT32(0) |
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71 | |
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72 | /** @} */ |
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73 | |
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74 | /** |
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75 | * @name EMC AHB Timeout Register (EMCAHBTimeOut) |
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76 | * |
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77 | * @{ |
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78 | */ |
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79 | |
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80 | #define EMC_AHB_TIMEOUT(val) BSP_FLD32(val, 0, 9) |
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81 | |
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82 | /** @} */ |
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83 | |
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84 | /** |
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85 | * @name SDRAM Mode and Extended Mode Registers |
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86 | * |
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87 | * @{ |
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88 | */ |
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89 | |
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90 | #define SDRAM_ADDR_ROW_16MB(val) ((uint32_t) (val) << 10) |
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91 | #define SDRAM_ADDR_ROW_32MB(val) ((uint32_t) (val) << 11) |
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92 | #define SDRAM_ADDR_ROW_64MB(val) ((uint32_t) (val) << 11) |
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93 | |
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94 | #define SDRAM_ADDR_BANK_16MB(ba1, ba0) \ |
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95 | (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 22)) |
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96 | #define SDRAM_ADDR_BANK_32MB(ba1, ba0) \ |
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97 | (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 24)) |
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98 | #define SDRAM_ADDR_BANK_64MB(ba1, ba0) \ |
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99 | (((uint32_t) (ba1) << 25) | ((uint32_t) (ba0) << 24)) |
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100 | |
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101 | #define SDRAM_MODE_16MB(mode) \ |
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102 | (SDRAM_ADDR_BANK_16MB(0, 0) | SDRAM_ADDR_ROW_16MB(mode)) |
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103 | #define SDRAM_MODE_32MB(mode) \ |
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104 | (SDRAM_ADDR_BANK_32MB(0, 0) | SDRAM_ADDR_ROW_32MB(mode)) |
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105 | #define SDRAM_MODE_64MB(mode) \ |
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106 | (SDRAM_ADDR_BANK_64MB(0, 0) | SDRAM_ADDR_ROW_64MB(mode)) |
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107 | |
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108 | #define SDRAM_EXTMODE_16MB(mode) \ |
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109 | (SDRAM_ADDR_BANK_16MB(1, 0) | SDRAM_ADDR_ROW_16MB(mode)) |
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110 | #define SDRAM_EXTMODE_32MB(mode) \ |
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111 | (SDRAM_ADDR_BANK_32MB(1, 0) | SDRAM_ADDR_ROW_32MB(mode)) |
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112 | #define SDRAM_EXTMODE_64MB(mode) \ |
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113 | (SDRAM_ADDR_BANK_64MB(1, 0) | SDRAM_ADDR_ROW_64MB(mode)) |
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114 | |
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115 | #define SDRAM_MODE_BURST_LENGTH(val) BSP_FLD32(val, 0, 2) |
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116 | #define SDRAM_MODE_BURST_INTERLEAVE BSP_BIT32(3) |
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117 | #define SDRAM_MODE_CAS(val) BSP_FLD32(val, 4, 6) |
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118 | #define SDRAM_MODE_TEST_MODE(val) BSP_FLD32(val, 7, 8) |
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119 | #define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BSP_BIT32(9) |
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120 | |
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121 | #define SDRAM_EXTMODE_PASR(val) BSP_FLD32(val, 0, 2) |
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122 | #define SDRAM_EXTMODE_DRIVER_STRENGTH(val) BSP_FLD32(val, 5, 6) |
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123 | |
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124 | /** @} */ |
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125 | |
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126 | typedef struct { |
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127 | uint32_t size; |
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128 | uint32_t config; |
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129 | uint32_t rascas; |
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130 | uint32_t mode; |
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131 | uint32_t extmode; |
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132 | } lpc32xx_emc_dynamic_chip_config; |
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133 | |
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134 | typedef struct { |
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135 | uint32_t sdramclk_ctrl; |
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136 | uint32_t nop_time_in_us; |
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137 | uint32_t control; |
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138 | uint32_t refresh; |
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139 | uint32_t readconfig; |
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140 | uint32_t trp; |
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141 | uint32_t tras; |
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142 | uint32_t tsrex; |
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143 | uint32_t twr; |
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144 | uint32_t trc; |
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145 | uint32_t trfc; |
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146 | uint32_t txsr; |
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147 | uint32_t trrd; |
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148 | uint32_t tmrd; |
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149 | uint32_t tcdlr; |
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150 | lpc32xx_emc_dynamic_chip_config chip [EMC_DYN_CHIP_COUNT]; |
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151 | } lpc32xx_emc_dynamic_config; |
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152 | |
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153 | void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg); |
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154 | |
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155 | /** @} */ |
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156 | |
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157 | #ifdef __cplusplus |
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158 | } |
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159 | #endif /* __cplusplus */ |
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160 | |
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161 | #endif /* LIBBSP_ARM_LPC32XX_EMC_H */ |
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