source: rtems/bsps/arm/lpc32xx/include/bsp/boot.h

Last change on this file was bcef89f2, checked in by Sebastian Huber <sebastian.huber@…>, on 05/19/23 at 06:18:25

Update company name

The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.

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File size: 3.4 KB
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup lpc32xx_boot
7 *
8 * @brief Boot support API.
9 */
10
11/*
12 * Copyright (c) 2010 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 *    notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 *    notice, this list of conditions and the following disclaimer in the
21 *    documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_ARM_LPC32XX_BOOT_H
37#define LIBBSP_ARM_LPC32XX_BOOT_H
38
39#include <stdint.h>
40
41#ifdef __cplusplus
42extern "C" {
43#endif /* __cplusplus */
44
45/**
46 * @defgroup lpc32xx_boot Boot Support
47 *
48 * @ingroup RTEMSBSPsARMLPC32XX
49 *
50 * @brief Boot support.
51 *
52 * The NXP internal boot program shall be the "stage-0 program".
53 *
54 * The boot program within the first page of the first or second block shall be
55 * "stage-1 program".  It will be invoked by the stage-0 program from NXP.
56 *
57 * The program loaded by the stage-1 program will be the "stage-2 program" or the
58 * "boot loader".
59 *
60 * The program loaded by the stage-2 program will be the "stage-3 program" or the
61 * "application".
62 *
63 * The stage-1 program image must have a format specified by NXP.
64 *
65 * The stage-2 and stage-3 program images may have any format.
66 *
67 * @{
68 */
69
70#define LPC32XX_BOOT_BLOCK_0 0
71#define LPC32XX_BOOT_BLOCK_1 1
72
73#define LPC32XX_BOOT_ICR_SP_3AC_8IF 0xf0
74#define LPC32XX_BOOT_ICR_SP_4AC_8IF 0xd2
75#define LPC32XX_BOOT_ICR_LP_4AC_8IF 0xb4
76#define LPC32XX_BOOT_ICR_LP_5AC_8IF 0x96
77
78typedef union {
79  struct {
80    uint8_t d0;
81    uint8_t reserved_0 [3];
82    uint8_t d1;
83    uint8_t reserved_1 [3];
84    uint8_t d2;
85    uint8_t reserved_2 [3];
86    uint8_t d3;
87    uint8_t reserved_3 [3];
88    uint8_t d4;
89    uint8_t reserved_4 [3];
90    uint8_t d5;
91    uint8_t reserved_5 [3];
92    uint8_t d6;
93    uint8_t reserved_6 [3];
94    uint8_t d7;
95    uint8_t reserved_7 [3];
96    uint8_t d8;
97    uint8_t reserved_8 [3];
98    uint8_t d9;
99    uint8_t reserved_9 [3];
100    uint8_t d10;
101    uint8_t reserved_10 [3];
102    uint8_t d11;
103    uint8_t reserved_11 [3];
104    uint8_t d12;
105    uint8_t reserved_12 [463];
106  } field;
107  uint32_t data [128];
108} lpc32xx_boot_block;
109
110void lpc32xx_setup_boot_block(
111  lpc32xx_boot_block *boot_block,
112  uint8_t icr,
113  uint8_t page_count
114);
115
116void lpc32xx_set_boot_block_bad(
117  lpc32xx_boot_block *boot_block
118);
119
120/** @} */
121
122#ifdef __cplusplus
123}
124#endif /* __cplusplus */
125
126#endif /* LIBBSP_ARM_LPC32XX_BOOT_H */
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