source: rtems/bsps/arm/lpc32xx/include/bsp.h @ 76ac42ff

Last change on this file since 76ac42ff was 76ac42ff, checked in by Joel Sherrill <joel@…>, on Aug 29, 2018 at 5:36:18 PM

lpc32xx/include/bsp.h: Resolve set but not used warning

  • Property mode set to 100644
File size: 5.5 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup arm_lpc32xx
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_LPC32XX_BSP_H
24#define LIBBSP_ARM_LPC32XX_BSP_H
25
26#include <bspopts.h>
27
28#define BSP_FEATURE_IRQ_EXTENSION
29
30#ifndef ASM
31
32#include <rtems.h>
33
34#include <bsp/lpc32xx.h>
35#include <bsp/default-initial-extension.h>
36
37#ifdef __cplusplus
38extern "C" {
39#endif /* __cplusplus */
40
41struct rtems_bsdnet_ifconfig;
42
43/**
44 * @defgroup arm_lpc32xx LPC32XX Support
45 *
46 * @ingroup bsp_arm
47 *
48 * @brief LPC32XX support package.
49 *
50 * @{
51 */
52
53/**
54 * @brief Network driver attach and detach function.
55 */
56int lpc_eth_attach_detach(
57  struct rtems_bsdnet_ifconfig *config,
58  int attaching
59);
60
61/**
62 * @brief Standard network driver attach and detach function.
63 */
64#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
65
66/**
67 * @brief Standard network driver name.
68 */
69#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
70
71/**
72 * @brief Optimized idle task.
73 *
74 * This idle task sets the power mode to idle.  This causes the processor clock
75 * to be stopped, while on-chip peripherals remain active.  Any enabled
76 * interrupt from a peripheral or an external interrupt source will cause the
77 * processor to resume execution.
78 *
79 * To enable the idle task use the following in the system configuration:
80 *
81 * @code
82 * #include <bsp.h>
83 *
84 * #define CONFIGURE_INIT
85 *
86 * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle
87 *
88 * #include <confdefs.h>
89 * @endcode
90 */
91void *lpc32xx_idle(uintptr_t ignored);
92
93#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1)
94
95static inline unsigned lpc32xx_timer(void)
96{
97  volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
98
99  return timer->tc;
100}
101
102static inline void lpc32xx_micro_seconds_delay(unsigned us)
103{
104  unsigned start = lpc32xx_timer();
105  unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000);
106  unsigned elapsed = 0;
107
108  do {
109    elapsed = lpc32xx_timer() - start;
110  } while (elapsed < delay);
111}
112
113#if LPC32XX_OSCILLATOR_MAIN == 13000000U
114  #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \
115    (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1))
116  #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \
117    (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0))
118#else
119  #error "unexpected main oscillator frequency"
120#endif
121
122bool lpc32xx_start_pll_setup(
123  uint32_t hclkpll_ctrl,
124  uint32_t hclkdiv_ctrl,
125  bool force
126);
127
128uint32_t lpc32xx_sysclk(void);
129
130uint32_t lpc32xx_hclkpll_clk(void);
131
132uint32_t lpc32xx_periph_clk(void);
133
134uint32_t lpc32xx_hclk(void);
135
136uint32_t lpc32xx_arm_clk(void);
137
138uint32_t lpc32xx_ddram_clk(void);
139
140typedef enum {
141  LPC32XX_NAND_CONTROLLER_NONE,
142  LPC32XX_NAND_CONTROLLER_MLC,
143  LPC32XX_NAND_CONTROLLER_SLC
144} lpc32xx_nand_controller;
145
146void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller);
147
148void bsp_restart(void *addr);
149
150void *bsp_idle_thread(uintptr_t arg);
151
152#define BSP_IDLE_TASK_BODY bsp_idle_thread
153
154#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5
155
156/**
157 * @brief Begin of magic zero area.
158 *
159 * A read from this area returns zero.  Writes have no effect.
160 */
161extern uint32_t lpc32xx_magic_zero_begin [];
162
163/**
164 * @brief End of magic zero area.
165 *
166 * A read from this area returns zero.  Writes have no effect.
167 */
168extern uint32_t lpc32xx_magic_zero_end [];
169
170/**
171 * @brief Size of magic zero area.
172 *
173 * A read from this area returns zero.  Writes have no effect.
174 */
175extern uint32_t lpc32xx_magic_zero_size [];
176
177#ifdef LPC32XX_SCRATCH_AREA_SIZE
178  /**
179   * @rief Scratch area.
180   *
181   * The usage is application specific.
182   */
183  extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE]
184    __attribute__((aligned(32)));
185#endif
186
187#define LPC32XX_DO_STOP_GPDMA \
188  do { \
189    if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \
190      if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \
191        int i = 0; \
192        for (i = 0; i < 8; ++i) { \
193          lpc32xx.dma.channels [i].cfg = 0; \
194        } \
195        lpc32xx.dma.cfg &= ~DMA_CFG_E; \
196      } \
197      LPC32XX_DMACLK_CTRL = 0; \
198    } \
199  } while (0)
200
201#define LPC32XX_DO_STOP_ETHERNET \
202  do { \
203    if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \
204      lpc32xx.eth.command = 0x38; \
205      lpc32xx.eth.mac1 = 0xcf00; \
206      lpc32xx.eth.mac1 = 0; \
207      LPC32XX_MAC_CLK_CTRL = 0; \
208    } \
209  } while (0)
210
211#define LPC32XX_DO_STOP_USB \
212  do { \
213    if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \
214      LPC32XX_OTG_CLK_CTRL = 0; \
215      LPC32XX_USB_CTRL = 0x80000; \
216    } \
217  } while (0)
218
219#define LPC32XX_DO_RESTART(addr) \
220  do { \
221    ARM_SWITCH_REGISTERS; \
222    rtems_interrupt_level level; \
223    uint32_t ctrl = 0; \
224  \
225    rtems_interrupt_disable(level); \
226    (void) level; /* avoid set but not used warning */ \
227  \
228    arm_cp15_data_cache_test_and_clean(); \
229    arm_cp15_instruction_cache_invalidate(); \
230  \
231    ctrl = arm_cp15_get_control(); \
232    ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \
233    arm_cp15_set_control(ctrl); \
234  \
235    __asm__ volatile ( \
236      ARM_SWITCH_TO_ARM \
237      "mov pc, %[addr]\n" \
238      ARM_SWITCH_BACK \
239      : ARM_SWITCH_OUTPUT \
240      : [addr] "r" (addr) \
241    ); \
242  } while (0)
243
244/** @} */
245
246/**
247 * @defgroup lpc LPC Support
248 *
249 * @ingroup arm_lpc32xx
250 *
251 * @brief LPC support package.
252 */
253
254#ifdef __cplusplus
255}
256#endif /* __cplusplus */
257
258#endif /* ASM */
259
260#endif /* LIBBSP_ARM_LPC32XX_BSP_H */
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