1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSBSPsARMLPC32XX |
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5 | * |
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6 | * @brief High speed UART driver (14-clock). |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/lpc32xx.h> |
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25 | #include <bsp/irq.h> |
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26 | #include <bsp/hsu.h> |
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27 | |
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28 | #define HSU_FIFO_SIZE 64 |
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29 | |
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30 | #define HSU_LEVEL_RX_MASK 0xffU |
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31 | #define HSU_LEVEL_TX_MASK 0xff00U |
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32 | #define HSU_LEVEL_TX_SHIFT 8 |
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33 | |
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34 | #define HSU_RX_DATA_MASK 0xffU |
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35 | #define HSU_RX_EMPTY (1U << 8) |
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36 | #define HSU_RX_ERROR (1U << 9) |
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37 | #define HSU_RX_BREAK (1U << 10) |
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38 | |
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39 | #define HSU_IIR_TX (1U << 0) |
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40 | #define HSU_IIR_RX_TRIG (1U << 1) |
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41 | #define HSU_IIR_RX_TIMEOUT (1U << 2) |
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42 | |
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43 | #define HSU_CTRL_INTR_DISABLED 0x1280fU |
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44 | #define HSU_CTRL_RX_INTR_ENABLED 0x1284fU |
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45 | #define HSU_CTRL_RX_AND_TX_INTR_ENABLED 0x1286fU |
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46 | |
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47 | /* We are interested in RX timeout, RX trigger and TX trigger interrupts */ |
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48 | #define HSU_IIR_MASK 0x7U |
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49 | |
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50 | bool lpc32xx_hsu_probe(rtems_termios_device_context *base) |
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51 | { |
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52 | lpc32xx_hsu_context *ctx = (lpc32xx_hsu_context *) base; |
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53 | volatile lpc32xx_hsu *hsu = ctx->hsu; |
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54 | |
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55 | hsu->ctrl = HSU_CTRL_INTR_DISABLED; |
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56 | |
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57 | /* Drain FIFOs */ |
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58 | while (hsu->level != 0) { |
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59 | hsu->fifo; |
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60 | } |
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61 | |
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62 | return true; |
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63 | } |
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64 | |
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65 | static void lpc32xx_hsu_interrupt_handler(void *arg) |
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66 | { |
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67 | rtems_termios_tty *tty = arg; |
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68 | lpc32xx_hsu_context *ctx = rtems_termios_get_device_context(tty); |
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69 | volatile lpc32xx_hsu *hsu = ctx->hsu; |
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70 | |
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71 | /* Iterate until no more interrupts are pending */ |
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72 | do { |
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73 | int rv = 0; |
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74 | int i = 0; |
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75 | char buf [HSU_FIFO_SIZE]; |
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76 | |
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77 | /* Enqueue received characters */ |
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78 | while (i < HSU_FIFO_SIZE) { |
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79 | uint32_t in = hsu->fifo; |
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80 | |
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81 | if ((in & HSU_RX_EMPTY) == 0) { |
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82 | if ((in & HSU_RX_BREAK) == 0) { |
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83 | buf [i] = in & HSU_RX_DATA_MASK; |
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84 | ++i; |
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85 | } |
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86 | } else { |
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87 | break; |
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88 | } |
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89 | } |
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90 | rtems_termios_enqueue_raw_characters(tty, buf, i); |
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91 | |
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92 | /* Dequeue transmitted characters */ |
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93 | rv = rtems_termios_dequeue_characters(tty, (int) ctx->chars_in_transmission); |
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94 | if (rv == 0) { |
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95 | /* Nothing to transmit */ |
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96 | } |
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97 | } while ((hsu->iir & HSU_IIR_MASK) != 0); |
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98 | } |
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99 | |
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100 | static bool lpc32xx_hsu_first_open( |
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101 | struct rtems_termios_tty *tty, |
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102 | rtems_termios_device_context *base, |
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103 | struct termios *term, |
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104 | rtems_libio_open_close_args_t *args |
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105 | ) |
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106 | { |
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107 | lpc32xx_hsu_context *ctx = (lpc32xx_hsu_context *) base; |
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108 | volatile lpc32xx_hsu *hsu = ctx->hsu; |
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109 | rtems_status_code sc; |
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110 | bool ok; |
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111 | |
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112 | sc = rtems_interrupt_handler_install( |
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113 | ctx->irq, |
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114 | "HSU", |
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115 | RTEMS_INTERRUPT_UNIQUE, |
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116 | lpc32xx_hsu_interrupt_handler, |
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117 | tty |
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118 | ); |
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119 | ok = sc == RTEMS_SUCCESSFUL; |
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120 | |
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121 | if (ok) { |
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122 | rtems_termios_set_initial_baud(tty, ctx->initial_baud); |
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123 | hsu->ctrl = HSU_CTRL_RX_INTR_ENABLED; |
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124 | } |
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125 | |
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126 | return ok; |
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127 | } |
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128 | |
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129 | static void lpc32xx_hsu_last_close( |
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130 | struct rtems_termios_tty *tty, |
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131 | rtems_termios_device_context *base, |
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132 | rtems_libio_open_close_args_t *args |
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133 | ) |
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134 | { |
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135 | lpc32xx_hsu_context *ctx = (lpc32xx_hsu_context *) base; |
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136 | volatile lpc32xx_hsu *hsu = ctx->hsu; |
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137 | |
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138 | hsu->ctrl = HSU_CTRL_INTR_DISABLED; |
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139 | |
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140 | rtems_interrupt_handler_remove( |
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141 | ctx->irq, |
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142 | lpc32xx_hsu_interrupt_handler, |
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143 | tty |
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144 | ); |
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145 | } |
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146 | |
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147 | static void lpc32xx_hsu_write( |
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148 | rtems_termios_device_context *base, |
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149 | const char *buf, |
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150 | size_t len |
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151 | ) |
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152 | { |
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153 | lpc32xx_hsu_context *ctx = (lpc32xx_hsu_context *) base; |
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154 | volatile lpc32xx_hsu *hsu = ctx->hsu; |
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155 | size_t tx_level = (hsu->level & HSU_LEVEL_TX_MASK) >> HSU_LEVEL_TX_SHIFT; |
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156 | size_t tx_free = HSU_FIFO_SIZE - tx_level; |
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157 | size_t i = 0; |
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158 | size_t out = len > tx_free ? tx_free : len; |
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159 | |
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160 | for (i = 0; i < out; ++i) { |
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161 | hsu->fifo = buf [i]; |
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162 | } |
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163 | |
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164 | ctx->chars_in_transmission = out; |
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165 | |
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166 | if (len > 0) { |
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167 | hsu->ctrl = HSU_CTRL_RX_AND_TX_INTR_ENABLED; |
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168 | } else { |
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169 | hsu->ctrl = HSU_CTRL_RX_INTR_ENABLED; |
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170 | hsu->iir = HSU_IIR_TX; |
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171 | } |
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172 | } |
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173 | |
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174 | static bool lpc32xx_hsu_set_attributes( |
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175 | rtems_termios_device_context *base, |
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176 | const struct termios *term |
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177 | ) |
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178 | { |
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179 | lpc32xx_hsu_context *ctx = (lpc32xx_hsu_context *) base; |
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180 | volatile lpc32xx_hsu *hsu = ctx->hsu; |
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181 | int baud_flags = term->c_ospeed; |
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182 | |
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183 | if (baud_flags != 0) { |
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184 | int32_t baud = rtems_termios_baud_to_number(baud_flags); |
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185 | |
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186 | if (baud > 0) { |
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187 | uint32_t baud_divisor = 14 * (uint32_t) baud; |
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188 | uint32_t rate = LPC32XX_PERIPH_CLK / baud_divisor; |
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189 | uint32_t remainder = LPC32XX_PERIPH_CLK - rate * baud_divisor; |
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190 | |
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191 | if (2 * remainder >= baud_divisor) { |
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192 | ++rate; |
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193 | } |
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194 | |
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195 | hsu->rate = rate - 1; |
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196 | } |
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197 | } |
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198 | |
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199 | return true; |
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200 | } |
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201 | |
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202 | const rtems_termios_device_handler lpc32xx_hsu_fns = { |
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203 | .first_open = lpc32xx_hsu_first_open, |
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204 | .last_close = lpc32xx_hsu_last_close, |
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205 | .write = lpc32xx_hsu_write, |
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206 | .set_attributes = lpc32xx_hsu_set_attributes, |
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207 | .mode = TERMIOS_IRQ_DRIVEN |
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208 | }; |
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