source: rtems/bsps/arm/lpc24xx/start/start-config-emc-dynamic.c @ cf5d5d80

Last change on this file since cf5d5d80 was cf5d5d80, checked in by Sebastian Huber <sebastian.huber@…>, on May 9, 2019 at 10:31:31 AM

bsp/lpc24xx: Fix dynamic EMC configurations

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1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsARMLPC24XX
5 *
6 * @brief BSP start EMC dynamic memory configuration.
7 */
8
9/*
10 * Copyright (c) 2011, 2019 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <bsp/start-config.h>
24#include <bsp/lpc24xx.h>
25
26/*
27 * FIXME: The NXP example code uses different values for the following two
28 * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
29 * how these values are determined.  The values from the NXP example code do
30 * not work.
31 */
32
33/* Use command delayed strategy */
34#define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1
35
36#define LPC24XX_EMCDLYCTL_DEFAULT 0x1112
37
38BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
39  lpc24xx_start_config_emc_dynamic [] = {
40#if defined(LPC24XX_EMC_MT48LC4M16A2)
41  /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
42  {
43    /* 15.6 us */
44    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
45
46    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
47
48    /* Precharge command period 20 ns */
49    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
50
51    /* Active to precharge command period 44 ns */
52    .tras = LPC24XX_PS_TO_EMCCLK(44000, 1),
53
54    /*
55     * UM: "devices without this parameter you use the same value as tXSR"
56     *
57     * The tXSR is 75 ns.
58     */
59    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
60
61    /*
62     * Forum: "tAPR, not in datasheet, if fail, use tRCD val"
63     *
64     * The tRCD is 20 ns */
65    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
66
67    /* Data-in to active command period tWR + tRP */
68    .tdal = LPC24XX_PS_TO_EMCCLK(15000 + 20000, 0),
69
70    /* Write recovery time 15 ns or 1 CLK + 7.5ns */
71    .twr = LPC24XX_PS_TO_EMCCLK(15000, 1),
72
73    /* Active to active command period 66 ns */
74    .trc = LPC24XX_PS_TO_EMCCLK(66000, 1),
75
76    /* Auto refresh period 66 ns */
77    .trfc = LPC24XX_PS_TO_EMCCLK(66000, 1),
78
79    /* Exit self refresh to active command period 75 ns */
80    .txsr = LPC24XX_PS_TO_EMCCLK(75000, 1),
81
82    /* Active bank a to active bank b command period 15 ns */
83    .trrd = LPC24XX_PS_TO_EMCCLK(15000, 1),
84
85    /* Load mode register to active or refresh command period 2 tCK */
86    .tmrd = 1, /* + 1 */
87
88    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
89  }
90#elif defined(LPC24XX_EMC_IS42S32800D7)
91  /* Dynamic Memory 0: ISSI IS42S32800D7 */
92  {
93    /* 15.6 us */
94    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
95
96    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
97
98    /* 20ns */
99    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
100
101    /* 45ns */
102    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
103
104    /* 70ns (tXSR) */
105    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
106
107    /* 20ns (tRCD) */
108    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
109
110    /* n clock cycles -> 38.8ns >= 35ns */
111    .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
112
113    /* 14ns (tDPL) */
114    .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
115
116    /* 67.5ns */
117    .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
118
119    /* 67.5ns (tRC) */
120    .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
121
122    /* 70ns */
123    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
124
125    /* 14ns */
126    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
127
128    /* 14ns */
129    .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
130
131    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
132  }
133#elif defined(LPC24XX_EMC_W9825G2JB75I)
134  /* Dynamic Memory 0: Winbond W9825G2JB75I */
135  {
136    /* 15.6 us */
137    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
138
139    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
140
141    /* 20ns */
142    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
143
144    /* 45ns */
145    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
146
147    /* 75ns (tXSR) */
148    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
149
150    /* 20ns (tRCD) */
151    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
152
153    /* tWR + tRP -> 2 * tCK + 20ns */
154    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
155
156    /* (n + 1) clock cycles == 2 * tCK */
157    .twr = 1,
158
159    /* 65ns */
160    .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
161
162    /* 65ns (tRC) */
163    .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
164
165    /* 75ns */
166    .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
167
168    /* (n + 1) clock cycles == 2 * tCK */
169    .trrd = 1,
170
171    /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
172    .tmrd = 1,
173
174    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
175  }
176#elif defined(LPC24XX_EMC_K4S561632E)
177  {
178    .refresh = 35,
179    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
180    .trp = 2,
181    .tras = 4,
182    .tsrex = 5,
183    .tapr = 1,
184    .tdal = 5,
185    .twr = 3,
186    .trc = 5,
187    .trfc = 5,
188    .txsr = 5,
189    .trrd = 3,
190    .tmrd = 2,
191    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
192  }
193#elif defined(LPC24XX_EMC_IS42S32800B)
194  {
195    /* 15.6us */
196    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
197
198    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
199
200    /* 20ns */
201    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
202
203    /* 45ns */
204    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
205
206    /* 70ns (tRC) */
207    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
208
209    /* FIXME */
210    .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
211
212    /* tWR + tRP -> 2 * tCK + 20ns */
213    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
214
215    /* (n + 1) clock cycles == 2 * tCK */
216    .twr = 1,
217
218    /* 70ns */
219    .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
220
221    /* 70ns */
222    .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
223
224    /* 70ns (tRC) */
225    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
226
227    /* 14ns */
228    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
229
230    /* (n + 1) clock cycles == 2 * tCK */
231    .tmrd = 1,
232
233    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
234  }
235#endif
236};
237
238/*
239 * Mode shift is determined for RBC by:
240 *
241 *   bus width in bits / 16 + bank bits + column bits
242 *
243 * Mode shift is determined for BRC by:
244 *
245 *   bus width in bits / 16 + column bits
246 */
247BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
248  lpc24xx_start_config_emc_dynamic_chip [] = {
249#if defined(LPC24XX_EMC_MT48LC4M16A2)
250  {
251    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
252
253    /*
254     * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
255     * writes.  4 banks, 12 row lines, 8 column lines, RBC.
256     */
257    .config = 0x280,
258
259    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
260    .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
261  }
262#elif defined(LPC24XX_EMC_W9825G2JB75I) \
263  || defined(LPC24XX_EMC_IS42S32800D7) \
264  || defined(LPC24XX_EMC_IS42S32800B)
265  {
266    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
267
268    /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
269    .config = 0x4480,
270
271    /* RAS based on tRCD = 20ns */
272    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
273
274    /* CAS 2, burst length 4 */
275    .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
276  }
277#elif defined(LPC24XX_EMC_K4S561632E)
278  {
279    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
280    .config = 0x680,
281    .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
282    .mode = 0xa0000000 | (0x33 << 12)
283  }
284#endif
285};
286
287BSP_START_DATA_SECTION const size_t
288  lpc24xx_start_config_emc_dynamic_chip_count =
289    sizeof(lpc24xx_start_config_emc_dynamic_chip)
290      / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
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