source: rtems/bsps/arm/lpc24xx/start/start-config-emc-dynamic.c @ c991eeec

Last change on this file since c991eeec was c991eeec, checked in by Sebastian Huber <sebastian.huber@…>, on Mar 4, 2019 at 2:32:15 PM

bsps: Adjust bsp.h Doxygen groups

Update #3706.

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1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsARMLPC24XX
5 *
6 * @brief BSP start EMC dynamic memory configuration.
7 */
8
9/*
10 * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <bsp/start-config.h>
24#include <bsp/lpc24xx.h>
25
26/*
27 * FIXME: The NXP example code uses different values for the follwing two
28 * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
29 * how these values are determined.  The values from the NXP example code do
30 * not work.
31 */
32
33/* Use command delayed strategy */
34#define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1
35
36#define LPC24XX_EMCDLYCTL_DEFAULT 0x1112
37
38BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
39  lpc24xx_start_config_emc_dynamic [] = {
40#if defined(LPC24XX_EMC_MT48LC4M16A2)
41  /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
42  {
43    /* 15.6 us */
44    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
45
46    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
47
48    /* Precharge command period 20 ns */
49    .trp = 1,
50
51    /* Active to precharge command period 44 ns */
52    .tras = 3,
53
54    /* FIXME */
55    .tsrex = 5,
56
57    /* FIXME */
58    .tapr = 2,
59
60    /* Data-in to active command period tWR + tRP */
61    .tdal = 4,
62
63    /* Write recovery time 15 ns */
64    .twr = 1,
65
66    /* Active to active command period 66 ns */
67    .trc = 4,
68
69    /* Auto refresh period 66 ns */
70    .trfc = 4,
71
72    /* Exit self refresh to active command period 75 ns */
73    .txsr = 5,
74
75    /* Active bank a to active bank b command period 15 ns */
76    .trrd = 1,
77
78    /* Load mode register to active or refresh command period 2 tCK */
79    .tmrd = 1
80  }
81#elif defined(LPC24XX_EMC_IS42S32800D7)
82  /* Dynamic Memory 0: ISSI IS42S32800D7 */
83  {
84    /* 15.6 us */
85    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
86
87    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
88
89    /* 20ns */
90    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
91
92    /* 45ns */
93    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
94
95    /* 70ns (tXSR) */
96    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
97
98    /* 20ns (tRCD) */
99    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
100
101    /* n clock cycles -> 38.8ns >= 35ns */
102    .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
103
104    /* 14ns (tDPL) */
105    .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
106
107    /* 67.5ns */
108    .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
109
110    /* 67.5ns (tRC) */
111    .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
112
113    /* 70ns */
114    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
115
116    /* 14ns */
117    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
118
119    /* 14ns */
120    .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
121
122    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
123  }
124#elif defined(LPC24XX_EMC_W9825G2JB75I)
125  /* Dynamic Memory 0: Winbond W9825G2JB75I */
126  {
127    /* 15.6 us */
128    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
129
130    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
131
132    /* 20ns */
133    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
134
135    /* 45ns */
136    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
137
138    /* 75ns (tXSR) */
139    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
140
141    /* 20ns (tRCD) */
142    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
143
144    /* tWR + tRP -> 2 * tCK + 20ns */
145    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
146
147    /* (n + 1) clock cycles == 2 * tCK */
148    .twr = 1,
149
150    /* 65ns */
151    .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
152
153    /* 65ns (tRC) */
154    .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
155
156    /* 75ns */
157    .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
158
159    /* (n + 1) clock cycles == 2 * tCK */
160    .trrd = 1,
161
162    /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
163    .tmrd = 1,
164
165    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
166  }
167#elif defined(LPC24XX_EMC_K4S561632E)
168  {
169    .refresh = 35,
170    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
171    .trp = 2,
172    .tras = 4,
173    .tsrex = 5,
174    .tapr = 1,
175    .tdal = 5,
176    .twr = 3,
177    .trc = 5,
178    .trfc = 5,
179    .txsr = 5,
180    .trrd = 3,
181    .tmrd = 2
182  }
183#elif defined(LPC24XX_EMC_IS42S32800B)
184  {
185    /* 15.6us */
186    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
187
188    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
189
190    /* 20ns */
191    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
192
193    /* 45ns */
194    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
195
196    /* 70ns (tRC) */
197    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
198
199    /* FIXME */
200    .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
201
202    /* tWR + tRP -> 2 * tCK + 20ns */
203    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
204
205    /* (n + 1) clock cycles == 2 * tCK */
206    .twr = 1,
207
208    /* 70ns */
209    .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
210
211    /* 70ns */
212    .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
213
214    /* 70ns (tRC) */
215    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
216
217    /* 14ns */
218    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
219
220    /* (n + 1) clock cycles == 2 * tCK */
221    .tmrd = 1,
222
223    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
224  }
225#endif
226};
227
228BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
229  lpc24xx_start_config_emc_dynamic_chip [] = {
230#if defined(LPC24XX_EMC_MT48LC4M16A2)
231  {
232    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
233
234    /*
235     * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
236     * writes.  4 banks, 12 row lines, 8 column lines.
237     */
238    .config = 0x280,
239
240    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
241    .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
242  }
243#elif defined(LPC24XX_EMC_W9825G2JB75I) \
244  || defined(LPC24XX_EMC_IS42S32800D7) \
245  || defined(LPC24XX_EMC_IS42S32800B)
246  {
247    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
248
249    /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
250    .config = 0x4480,
251
252    /* RAS based on tRCD = 20ns */
253    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
254
255    /* CAS 2, burst length 4 */
256    .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
257  }
258#elif defined(LPC24XX_EMC_K4S561632E)
259  {
260    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
261    .config = 0x680,
262    .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
263    .mode = 0xa0000000 | (0x33 << 12)
264  }
265#endif
266};
267
268BSP_START_DATA_SECTION const size_t
269  lpc24xx_start_config_emc_dynamic_chip_count =
270    sizeof(lpc24xx_start_config_emc_dynamic_chip)
271      / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
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