source: rtems/bsps/arm/lpc24xx/start/start-config-emc-dynamic.c @ 6cad529

Last change on this file since 6cad529 was 6cad529, checked in by Sebastian Huber <sebastian.huber@…>, on May 9, 2019 at 7:16:20 AM

bsp/lpc24xx: Add SDRAM mode settings comment

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1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsARMLPC24XX
5 *
6 * @brief BSP start EMC dynamic memory configuration.
7 */
8
9/*
10 * Copyright (c) 2011, 2019 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <bsp/start-config.h>
24#include <bsp/lpc24xx.h>
25
26/*
27 * FIXME: The NXP example code uses different values for the following two
28 * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
29 * how these values are determined.  The values from the NXP example code do
30 * not work.
31 */
32
33/* Use command delayed strategy */
34#define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1
35
36#define LPC24XX_EMCDLYCTL_DEFAULT 0x1112
37
38BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
39  lpc24xx_start_config_emc_dynamic [] = {
40#if defined(LPC24XX_EMC_MT48LC4M16A2)
41  /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
42  {
43    /* 15.6 us */
44    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
45
46    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
47
48    /* Precharge command period 20 ns */
49    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
50
51    /* Active to precharge command period 44 ns */
52    .tras = LPC24XX_PS_TO_EMCCLK(44000, 1),
53
54    /*
55     * UM: "devices without this parameter you use the same value as tXSR"
56     *
57     * The tXSR is 75 ns.
58     */
59    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
60
61    /*
62     * Forum: "tAPR, not in datasheet, if fail, use tRCD val"
63     *
64     * The tRCD is 20 ns */
65    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
66
67    /* Data-in to active command period tWR + tRP */
68    .tdal = LPC24XX_PS_TO_EMCCLK(15000 + 20000, 0),
69
70    /* Write recovery time 15 ns or 1 CLK + 7.5ns */
71    .twr = LPC24XX_PS_TO_EMCCLK(15000, 1),
72
73    /* Active to active command period 66 ns */
74    .trc = LPC24XX_PS_TO_EMCCLK(66000, 1),
75
76    /* Auto refresh period 66 ns */
77    .trfc = LPC24XX_PS_TO_EMCCLK(66000, 1),
78
79    /* Exit self refresh to active command period 75 ns */
80    .txsr = LPC24XX_PS_TO_EMCCLK(75000, 1),
81
82    /* Active bank a to active bank b command period 15 ns */
83    .trrd = LPC24XX_PS_TO_EMCCLK(15000, 1),
84
85    /* Load mode register to active or refresh command period 2 tCK */
86    .tmrd = 1 /* + 1 */
87  }
88#elif defined(LPC24XX_EMC_IS42S32800D7)
89  /* Dynamic Memory 0: ISSI IS42S32800D7 */
90  {
91    /* 15.6 us */
92    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
93
94    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
95
96    /* 20ns */
97    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
98
99    /* 45ns */
100    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
101
102    /* 70ns (tXSR) */
103    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
104
105    /* 20ns (tRCD) */
106    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
107
108    /* n clock cycles -> 38.8ns >= 35ns */
109    .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
110
111    /* 14ns (tDPL) */
112    .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
113
114    /* 67.5ns */
115    .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
116
117    /* 67.5ns (tRC) */
118    .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
119
120    /* 70ns */
121    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
122
123    /* 14ns */
124    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
125
126    /* 14ns */
127    .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
128
129    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
130  }
131#elif defined(LPC24XX_EMC_W9825G2JB75I)
132  /* Dynamic Memory 0: Winbond W9825G2JB75I */
133  {
134    /* 15.6 us */
135    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
136
137    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
138
139    /* 20ns */
140    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
141
142    /* 45ns */
143    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
144
145    /* 75ns (tXSR) */
146    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
147
148    /* 20ns (tRCD) */
149    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
150
151    /* tWR + tRP -> 2 * tCK + 20ns */
152    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
153
154    /* (n + 1) clock cycles == 2 * tCK */
155    .twr = 1,
156
157    /* 65ns */
158    .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
159
160    /* 65ns (tRC) */
161    .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
162
163    /* 75ns */
164    .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
165
166    /* (n + 1) clock cycles == 2 * tCK */
167    .trrd = 1,
168
169    /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
170    .tmrd = 1,
171
172    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
173  }
174#elif defined(LPC24XX_EMC_K4S561632E)
175  {
176    .refresh = 35,
177    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
178    .trp = 2,
179    .tras = 4,
180    .tsrex = 5,
181    .tapr = 1,
182    .tdal = 5,
183    .twr = 3,
184    .trc = 5,
185    .trfc = 5,
186    .txsr = 5,
187    .trrd = 3,
188    .tmrd = 2
189  }
190#elif defined(LPC24XX_EMC_IS42S32800B)
191  {
192    /* 15.6us */
193    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
194
195    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
196
197    /* 20ns */
198    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
199
200    /* 45ns */
201    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
202
203    /* 70ns (tRC) */
204    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
205
206    /* FIXME */
207    .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
208
209    /* tWR + tRP -> 2 * tCK + 20ns */
210    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
211
212    /* (n + 1) clock cycles == 2 * tCK */
213    .twr = 1,
214
215    /* 70ns */
216    .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
217
218    /* 70ns */
219    .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
220
221    /* 70ns (tRC) */
222    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
223
224    /* 14ns */
225    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
226
227    /* (n + 1) clock cycles == 2 * tCK */
228    .tmrd = 1,
229
230    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
231  }
232#endif
233};
234
235/*
236 * Mode shift is determined for RBC by:
237 *
238 *   bus width in bits / 16 + bank bits + column bits
239 *
240 * Mode shift is determined for BRC by:
241 *
242 *   bus width in bits / 16 + column bits
243 */
244BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
245  lpc24xx_start_config_emc_dynamic_chip [] = {
246#if defined(LPC24XX_EMC_MT48LC4M16A2)
247  {
248    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
249
250    /*
251     * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
252     * writes.  4 banks, 12 row lines, 8 column lines, RBC.
253     */
254    .config = 0x280,
255
256    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
257    .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
258  }
259#elif defined(LPC24XX_EMC_W9825G2JB75I) \
260  || defined(LPC24XX_EMC_IS42S32800D7) \
261  || defined(LPC24XX_EMC_IS42S32800B)
262  {
263    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
264
265    /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
266    .config = 0x4480,
267
268    /* RAS based on tRCD = 20ns */
269    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
270
271    /* CAS 2, burst length 4 */
272    .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
273  }
274#elif defined(LPC24XX_EMC_K4S561632E)
275  {
276    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
277    .config = 0x680,
278    .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
279    .mode = 0xa0000000 | (0x33 << 12)
280  }
281#endif
282};
283
284BSP_START_DATA_SECTION const size_t
285  lpc24xx_start_config_emc_dynamic_chip_count =
286    sizeof(lpc24xx_start_config_emc_dynamic_chip)
287      / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
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