source: rtems/bsps/arm/lpc24xx/start/start-config-emc-dynamic.c

Last change on this file was bcef89f2, checked in by Sebastian Huber <sebastian.huber@…>, on 05/19/23 at 06:18:25

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1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup RTEMSBSPsARMLPC24XX
7 *
8 * @brief BSP start EMC dynamic memory configuration.
9 */
10
11/*
12 * Copyright (C) 2011, 2019 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 *    notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 *    notice, this list of conditions and the following disclaimer in the
21 *    documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include <bsp/start-config.h>
37#include <bsp/lpc24xx.h>
38
39/*
40 * FIXME: The NXP example code uses different values for the following two
41 * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
42 * how these values are determined.  The values from the NXP example code do
43 * not work.
44 */
45
46/* Use command delayed strategy */
47#define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1
48
49#define LPC24XX_EMCDLYCTL_DEFAULT 0x1112
50
51BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
52  lpc24xx_start_config_emc_dynamic [] = {
53#if defined(LPC24XX_EMC_MT48LC4M16A2)
54  /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
55  {
56    /* 15.6 us */
57    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
58
59    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
60
61    /* Precharge command period 20 ns */
62    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
63
64    /* Active to precharge command period 44 ns */
65    .tras = LPC24XX_PS_TO_EMCCLK(44000, 1),
66
67    /*
68     * UM: "devices without this parameter you use the same value as tXSR"
69     *
70     * The tXSR is 75 ns.
71     */
72    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
73
74    /*
75     * Forum: "tAPR, not in datasheet, if fail, use tRCD val"
76     *
77     * The tRCD is 20 ns */
78    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
79
80    /* Data-in to active command period tWR + tRP */
81    .tdal = LPC24XX_PS_TO_EMCCLK(15000 + 20000, 0),
82
83    /* Write recovery time 15 ns or 1 CLK + 7.5ns */
84    .twr = LPC24XX_PS_TO_EMCCLK(15000, 1),
85
86    /* Active to active command period 66 ns */
87    .trc = LPC24XX_PS_TO_EMCCLK(66000, 1),
88
89    /* Auto refresh period 66 ns */
90    .trfc = LPC24XX_PS_TO_EMCCLK(66000, 1),
91
92    /* Exit self refresh to active command period 75 ns */
93    .txsr = LPC24XX_PS_TO_EMCCLK(75000, 1),
94
95    /* Active bank a to active bank b command period 15 ns */
96    .trrd = LPC24XX_PS_TO_EMCCLK(15000, 1),
97
98    /* Load mode register to active or refresh command period 2 tCK */
99    .tmrd = 1, /* + 1 */
100
101    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
102  }
103#elif defined(LPC24XX_EMC_IS42S32800D7)
104  /* Dynamic Memory 0: ISSI IS42S32800D7 */
105  {
106    /* 15.6 us */
107    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
108
109    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
110
111    /* 20ns */
112    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
113
114    /* 45ns */
115    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
116
117    /* 70ns (tXSR) */
118    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
119
120    /* 20ns (tRCD) */
121    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
122
123    /* n clock cycles -> 38.8ns >= 35ns */
124    .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
125
126    /* 14ns (tDPL) */
127    .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
128
129    /* 67.5ns */
130    .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
131
132    /* 67.5ns (tRC) */
133    .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
134
135    /* 70ns */
136    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
137
138    /* 14ns */
139    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
140
141    /* 14ns */
142    .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
143
144    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
145  }
146#elif defined(LPC24XX_EMC_W9825G2JB75I)
147  /* Dynamic Memory 0: Winbond W9825G2JB75I */
148  {
149    /* 15.6 us */
150    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
151
152    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
153
154    /* 20ns */
155    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
156
157    /* 45ns */
158    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
159
160    /* 75ns (tXSR) */
161    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
162
163    /* 20ns (tRCD) */
164    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
165
166    /* tWR + tRP -> 2 * tCK + 20ns */
167    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
168
169    /* (n + 1) clock cycles == 2 * tCK */
170    .twr = 1,
171
172    /* 65ns */
173    .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
174
175    /* 65ns (tRC) */
176    .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
177
178    /* 75ns */
179    .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
180
181    /* (n + 1) clock cycles == 2 * tCK */
182    .trrd = 1,
183
184    /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
185    .tmrd = 1,
186
187    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
188  }
189#elif defined(LPC24XX_EMC_K4S561632E)
190  {
191    .refresh = 35,
192    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
193    .trp = 2,
194    .tras = 4,
195    .tsrex = 5,
196    .tapr = 1,
197    .tdal = 5,
198    .twr = 3,
199    .trc = 5,
200    .trfc = 5,
201    .txsr = 5,
202    .trrd = 3,
203    .tmrd = 2,
204    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
205  }
206#elif defined(LPC24XX_EMC_IS42S32800B)
207  {
208    /* 15.6us */
209    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
210
211    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
212
213    /* 20ns */
214    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
215
216    /* 45ns */
217    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
218
219    /* 70ns (tRC) */
220    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
221
222    /* FIXME */
223    .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
224
225    /* tWR + tRP -> 2 * tCK + 20ns */
226    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
227
228    /* (n + 1) clock cycles == 2 * tCK */
229    .twr = 1,
230
231    /* 70ns */
232    .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
233
234    /* 70ns */
235    .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
236
237    /* 70ns (tRC) */
238    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
239
240    /* 14ns */
241    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
242
243    /* (n + 1) clock cycles == 2 * tCK */
244    .tmrd = 1,
245
246    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
247  }
248#endif
249};
250
251/*
252 * Mode shift is determined for RBC by:
253 *
254 *   bus width in bits / 16 + bank bits + column bits
255 *
256 * Mode shift is determined for BRC by:
257 *
258 *   bus width in bits / 16 + column bits
259 */
260BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
261  lpc24xx_start_config_emc_dynamic_chip [] = {
262#if defined(LPC24XX_EMC_MT48LC4M16A2)
263  {
264    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
265
266    /*
267     * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
268     * writes.  4 banks, 12 row lines, 8 column lines, RBC.
269     */
270    .config = 0x280,
271
272    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
273    .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
274  }
275#elif defined(LPC24XX_EMC_W9825G2JB75I) \
276  || defined(LPC24XX_EMC_IS42S32800D7) \
277  || defined(LPC24XX_EMC_IS42S32800B)
278  {
279    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
280
281    /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
282    .config = 0x4480,
283
284    /* RAS based on tRCD = 20ns */
285    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
286
287    /* CAS 2, burst length 4 */
288    .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
289  }
290#elif defined(LPC24XX_EMC_K4S561632E)
291  {
292    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
293    .config = 0x680,
294    .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
295    .mode = 0xa0000000 | (0x33 << 12)
296  }
297#endif
298};
299
300BSP_START_DATA_SECTION const size_t
301  lpc24xx_start_config_emc_dynamic_chip_count =
302    sizeof(lpc24xx_start_config_emc_dynamic_chip)
303      / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
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