1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_interrupt |
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5 | * |
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6 | * @brief LPC24XX interrupt support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/license/LICENSE. |
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15 | */ |
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16 | |
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17 | #include <rtems/score/armv4.h> |
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18 | #include <rtems/score/armv7m.h> |
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19 | |
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20 | #include <bsp.h> |
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21 | #include <bsp/irq.h> |
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22 | #include <bsp/irq-generic.h> |
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23 | #include <bsp/lpc24xx.h> |
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24 | #include <bsp/linker-symbols.h> |
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25 | |
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26 | static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector) |
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27 | { |
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28 | return vector < BSP_INTERRUPT_VECTOR_COUNT; |
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29 | } |
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30 | |
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31 | void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority) |
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32 | { |
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33 | if (lpc24xx_irq_is_valid(vector)) { |
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34 | if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) { |
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35 | priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX; |
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36 | } |
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37 | |
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38 | #ifdef ARM_MULTILIB_ARCH_V4 |
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39 | VICVectPriorityBase [vector] = priority; |
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40 | #else |
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41 | _ARMV7M_NVIC_Set_priority((int) vector, (int) (priority << 3)); |
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42 | #endif |
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43 | } |
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44 | } |
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45 | |
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46 | unsigned lpc24xx_irq_get_priority(rtems_vector_number vector) |
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47 | { |
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48 | if (lpc24xx_irq_is_valid(vector)) { |
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49 | #ifdef ARM_MULTILIB_ARCH_V4 |
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50 | return VICVectPriorityBase [vector]; |
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51 | #else |
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52 | return (unsigned) (_ARMV7M_NVIC_Get_priority((int) vector) >> 3); |
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53 | #endif |
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54 | } else { |
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55 | return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U; |
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56 | } |
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57 | } |
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58 | |
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59 | #ifdef ARM_MULTILIB_ARCH_V4 |
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60 | |
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61 | rtems_status_code bsp_interrupt_get_attributes( |
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62 | rtems_vector_number vector, |
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63 | rtems_interrupt_attributes *attributes |
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64 | ) |
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65 | { |
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66 | return RTEMS_SUCCESSFUL; |
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67 | } |
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68 | |
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69 | rtems_status_code bsp_interrupt_is_pending( |
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70 | rtems_vector_number vector, |
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71 | bool *pending |
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72 | ) |
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73 | { |
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74 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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75 | bsp_interrupt_assert(pending != NULL); |
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76 | *pending = false; |
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77 | return RTEMS_UNSATISFIED; |
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78 | } |
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79 | |
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80 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
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81 | { |
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82 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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83 | return RTEMS_UNSATISFIED; |
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84 | } |
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85 | |
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86 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
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87 | { |
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88 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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89 | return RTEMS_UNSATISFIED; |
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90 | } |
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91 | |
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92 | rtems_status_code bsp_interrupt_vector_is_enabled( |
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93 | rtems_vector_number vector, |
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94 | bool *enabled |
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95 | ) |
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96 | { |
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97 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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98 | bsp_interrupt_assert(enabled != NULL); |
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99 | *enabled = false; |
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100 | return RTEMS_UNSATISFIED; |
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101 | } |
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102 | |
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103 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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104 | { |
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105 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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106 | VICIntEnable = 1U << vector; |
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107 | return RTEMS_SUCCESSFUL; |
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108 | } |
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109 | |
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110 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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111 | { |
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112 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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113 | VICIntEnClear = 1U << vector; |
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114 | return RTEMS_SUCCESSFUL; |
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115 | } |
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116 | |
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117 | void bsp_interrupt_facility_initialize(void) |
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118 | { |
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119 | volatile uint32_t *addr = VICVectAddrBase; |
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120 | volatile uint32_t *prio = VICVectPriorityBase; |
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121 | rtems_vector_number i = 0; |
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122 | |
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123 | /* Disable all interrupts */ |
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124 | VICIntEnClear = 0xffffffff; |
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125 | |
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126 | /* Clear all software interrupts */ |
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127 | VICSoftIntClear = 0xffffffff; |
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128 | |
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129 | /* Use IRQ category */ |
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130 | VICIntSelect = 0; |
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131 | |
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132 | for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) { |
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133 | /* Use the vector address register to store the vector number */ |
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134 | addr [i] = i; |
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135 | |
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136 | /* Give vector lowest priority */ |
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137 | prio [i] = 15; |
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138 | } |
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139 | |
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140 | /* Reset priority mask register */ |
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141 | VICSWPrioMask = 0xffff; |
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142 | |
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143 | /* Acknowledge interrupts for all priorities */ |
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144 | for ( |
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145 | i = LPC24XX_IRQ_PRIORITY_VALUE_MIN; |
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146 | i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX; |
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147 | ++i |
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148 | ) { |
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149 | VICVectAddr = 0; |
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150 | } |
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151 | |
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152 | /* Install the IRQ exception handler */ |
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153 | _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL); |
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154 | } |
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155 | |
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156 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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