source: rtems/bsps/arm/lpc24xx/irq/irq.c @ a3fe23c

5
Last change on this file since a3fe23c was 8f8ccee, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 23, 2018 at 7:50:39 AM

bsps: Move interrupt controller support to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup bsp_interrupt
5 *
6 * @brief LPC24XX interrupt support.
7 */
8
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <rtems/score/armv4.h>
24#include <rtems/score/armv7m.h>
25
26#include <bsp.h>
27#include <bsp/irq.h>
28#include <bsp/irq-generic.h>
29#include <bsp/lpc24xx.h>
30#include <bsp/linker-symbols.h>
31
32static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector)
33{
34  return vector <= BSP_INTERRUPT_VECTOR_MAX;
35}
36
37void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority)
38{
39  if (lpc24xx_irq_is_valid(vector)) {
40    if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) {
41      priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX;
42    }
43
44    #ifdef ARM_MULTILIB_ARCH_V4
45      VICVectPriorityBase [vector] = priority;
46    #else
47      _ARMV7M_NVIC_Set_priority((int) vector, (int) (priority << 3));
48    #endif
49  }
50}
51
52unsigned lpc24xx_irq_get_priority(rtems_vector_number vector)
53{
54  if (lpc24xx_irq_is_valid(vector)) {
55    #ifdef ARM_MULTILIB_ARCH_V4
56      return VICVectPriorityBase [vector];
57    #else
58      return (unsigned) (_ARMV7M_NVIC_Get_priority((int) vector) >> 3);
59    #endif
60  } else {
61    return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U;
62  }
63}
64
65#ifdef ARM_MULTILIB_ARCH_V4
66
67void bsp_interrupt_vector_enable(rtems_vector_number vector)
68{
69  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
70  VICIntEnable = 1U << vector;
71}
72
73void bsp_interrupt_vector_disable(rtems_vector_number vector)
74{
75  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
76  VICIntEnClear = 1U << vector;
77}
78
79rtems_status_code bsp_interrupt_facility_initialize(void)
80{
81  volatile uint32_t *addr = VICVectAddrBase;
82  volatile uint32_t *prio = VICVectPriorityBase;
83  rtems_vector_number i = 0;
84
85  /* Disable all interrupts */
86  VICIntEnClear = 0xffffffff;
87
88  /* Clear all software interrupts */
89  VICSoftIntClear = 0xffffffff;
90
91  /* Use IRQ category */
92  VICIntSelect = 0;
93
94  for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
95    /* Use the vector address register to store the vector number */
96    addr [i] = i;
97
98    /* Give vector lowest priority */
99    prio [i] = 15;
100  }
101
102  /* Reset priority mask register */
103  VICSWPrioMask = 0xffff;
104
105  /* Acknowledge interrupts for all priorities */
106  for (
107    i = LPC24XX_IRQ_PRIORITY_VALUE_MIN;
108    i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX;
109    ++i
110  ) {
111    VICVectAddr = 0;
112  }
113
114  /* Install the IRQ exception handler */
115  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
116
117  return RTEMS_SUCCESSFUL;
118}
119
120#endif /* ARM_MULTILIB_ARCH_V4 */
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