1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSImplClassicIntr |
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7 | * |
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8 | * @brief LPC24XX interrupt support. |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG |
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13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
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15 | * modification, are permitted provided that the following conditions |
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16 | * are met: |
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17 | * 1. Redistributions of source code must retain the above copyright |
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18 | * notice, this list of conditions and the following disclaimer. |
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19 | * 2. Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the distribution. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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27 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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33 | * POSSIBILITY OF SUCH DAMAGE. |
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34 | */ |
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35 | |
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36 | #include <rtems/score/armv4.h> |
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37 | #include <rtems/score/armv7m.h> |
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38 | |
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39 | #include <bsp.h> |
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40 | #include <bsp/irq.h> |
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41 | #include <bsp/irq-generic.h> |
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42 | #include <bsp/lpc24xx.h> |
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43 | #include <bsp/linker-symbols.h> |
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44 | |
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45 | static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector) |
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46 | { |
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47 | return vector < BSP_INTERRUPT_VECTOR_COUNT; |
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48 | } |
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49 | |
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50 | void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority) |
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51 | { |
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52 | if (lpc24xx_irq_is_valid(vector)) { |
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53 | if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) { |
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54 | priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX; |
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55 | } |
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56 | |
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57 | #ifdef ARM_MULTILIB_ARCH_V4 |
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58 | VICVectPriorityBase [vector] = priority; |
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59 | #else |
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60 | _ARMV7M_NVIC_Set_priority((int) vector, (int) (priority << 3)); |
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61 | #endif |
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62 | } |
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63 | } |
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64 | |
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65 | unsigned lpc24xx_irq_get_priority(rtems_vector_number vector) |
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66 | { |
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67 | if (lpc24xx_irq_is_valid(vector)) { |
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68 | #ifdef ARM_MULTILIB_ARCH_V4 |
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69 | return VICVectPriorityBase [vector]; |
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70 | #else |
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71 | return (unsigned) (_ARMV7M_NVIC_Get_priority((int) vector) >> 3); |
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72 | #endif |
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73 | } else { |
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74 | return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U; |
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75 | } |
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76 | } |
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77 | |
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78 | #ifdef ARM_MULTILIB_ARCH_V4 |
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79 | |
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80 | rtems_status_code bsp_interrupt_get_attributes( |
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81 | rtems_vector_number vector, |
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82 | rtems_interrupt_attributes *attributes |
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83 | ) |
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84 | { |
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85 | return RTEMS_SUCCESSFUL; |
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86 | } |
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87 | |
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88 | rtems_status_code bsp_interrupt_is_pending( |
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89 | rtems_vector_number vector, |
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90 | bool *pending |
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91 | ) |
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92 | { |
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93 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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94 | bsp_interrupt_assert(pending != NULL); |
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95 | *pending = false; |
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96 | return RTEMS_UNSATISFIED; |
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97 | } |
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98 | |
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99 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
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100 | { |
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101 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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102 | return RTEMS_UNSATISFIED; |
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103 | } |
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104 | |
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105 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
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106 | { |
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107 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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108 | return RTEMS_UNSATISFIED; |
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109 | } |
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110 | |
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111 | rtems_status_code bsp_interrupt_vector_is_enabled( |
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112 | rtems_vector_number vector, |
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113 | bool *enabled |
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114 | ) |
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115 | { |
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116 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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117 | bsp_interrupt_assert(enabled != NULL); |
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118 | *enabled = false; |
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119 | return RTEMS_UNSATISFIED; |
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120 | } |
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121 | |
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122 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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123 | { |
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124 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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125 | VICIntEnable = 1U << vector; |
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126 | return RTEMS_SUCCESSFUL; |
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127 | } |
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128 | |
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129 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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130 | { |
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131 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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132 | VICIntEnClear = 1U << vector; |
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133 | return RTEMS_SUCCESSFUL; |
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134 | } |
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135 | |
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136 | void bsp_interrupt_facility_initialize(void) |
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137 | { |
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138 | volatile uint32_t *addr = VICVectAddrBase; |
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139 | volatile uint32_t *prio = VICVectPriorityBase; |
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140 | rtems_vector_number i = 0; |
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141 | |
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142 | /* Disable all interrupts */ |
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143 | VICIntEnClear = 0xffffffff; |
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144 | |
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145 | /* Clear all software interrupts */ |
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146 | VICSoftIntClear = 0xffffffff; |
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147 | |
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148 | /* Use IRQ category */ |
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149 | VICIntSelect = 0; |
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150 | |
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151 | for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) { |
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152 | /* Use the vector address register to store the vector number */ |
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153 | addr [i] = i; |
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154 | |
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155 | /* Give vector lowest priority */ |
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156 | prio [i] = 15; |
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157 | } |
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158 | |
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159 | /* Reset priority mask register */ |
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160 | VICSWPrioMask = 0xffff; |
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161 | |
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162 | /* Acknowledge interrupts for all priorities */ |
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163 | for ( |
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164 | i = LPC24XX_IRQ_PRIORITY_VALUE_MIN; |
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165 | i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX; |
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166 | ++i |
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167 | ) { |
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168 | VICVectAddr = 0; |
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169 | } |
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170 | |
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171 | /* Install the IRQ exception handler */ |
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172 | _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL); |
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173 | } |
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174 | |
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175 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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