source: rtems/bsps/arm/lpc24xx/include/bsp/lpc17xx.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 7.8 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc24xx_regs
5 *
6 * @brief Register definitions.
7 */
8
9/*
10 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LPC17XX_REGS_H
24#define LPC17XX_REGS_H
25
26#include <bsp/utility.h>
27
28#define LPC17XX_BASE 0x00
29
30typedef struct {
31#define LPC17XX_WWDT_MOD_WDEN BSP_BIT32(0)
32#define LPC17XX_WWDT_MOD_WDRESET BSP_BIT32(1)
33#define LPC17XX_WWDT_MOD_WDTOF BSP_BIT32(2)
34#define LPC17XX_WWDT_MOD_WDINT BSP_BIT32(3)
35#define LPC17XX_WWDT_MOD_WDPROTECT BSP_BIT32(4)
36        uint32_t mod;
37        uint32_t tc;
38        uint32_t feed;
39        uint32_t tv;
40        uint32_t reserved_10;
41        uint32_t warnint;
42        uint32_t window;
43        uint32_t reserved_1c;
44} lpc17xx_wwdt;
45
46#define LPC17XX_WWDT (*(volatile lpc17xx_wwdt *) (LPC17XX_BASE + 0x40000000))
47
48typedef struct {
49#define LPC17XX_PLL_CON_PLLE BSP_BIT32(0)
50#define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4)
51#define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4)
52#define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
53#define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6)
54#define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6)
55#define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
56#define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8)
57#define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10)
58        uint32_t con;
59        uint32_t cfg;
60        uint32_t stat;
61        uint32_t feed;
62} lpc17xx_pll;
63
64typedef struct {
65        uint32_t flashcfg;
66#define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15)
67#define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15)
68#define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
69        uint32_t reserved_04 [15];
70        uint32_t memmap;
71#define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0)
72        uint32_t reserved_44 [15];
73        lpc17xx_pll pll_0;
74        uint32_t reserved_90 [4];
75        lpc17xx_pll pll_1;
76        uint32_t reserved_b0 [4];
77        uint32_t pcon;
78#define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0)
79#define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1)
80#define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2)
81#define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3)
82#define LPC17XX_SCB_PCON_BORD BSP_BIT32(4)
83#define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8)
84#define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9)
85#define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10)
86#define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11)
87        uint32_t pconp;
88#define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0)
89#define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1)
90#define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2)
91#define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3)
92#define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4)
93#define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5)
94#define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6)
95#define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7)
96#define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8)
97#define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9)
98#define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10)
99#define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11)
100#define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12)
101#define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13)
102#define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14)
103#define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15)
104#define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17)
105#define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18)
106#define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19)
107#define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20)
108#define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21)
109#define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22)
110#define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23)
111#define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24)
112#define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25)
113#define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26)
114#define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27)
115#define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28)
116#define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29)
117#define LPC17XX_SCB_PCONP_USB BSP_BIT32(30)
118#define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31)
119        uint32_t reserved_c8 [14];
120        uint32_t emcclksel;
121#define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0)
122        uint32_t cclksel;
123#define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4)
124#define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
125#define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
126#define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8)
127        uint32_t usbclksel;
128#define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4)
129#define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
130#define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
131#define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9)
132#define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9)
133#define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
134        uint32_t clksrcsel;
135#define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0)
136        uint32_t reserved_110 [12];
137        uint32_t extint;
138        uint32_t reserved_144;
139        uint32_t extmode;
140        uint32_t extpolar;
141        uint32_t reserved_150 [12];
142        uint32_t rsid;
143        uint32_t reserved_184 [1];
144        uint32_t matrixarb;
145        uint32_t reserved_18c [5];
146        uint32_t scs;
147#define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0)
148#define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1)
149#define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2)
150#define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3)
151#define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4)
152#define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5)
153#define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6)
154        uint32_t reserved_1a4;
155        uint32_t pclksel;
156#define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4)
157#define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
158#define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
159        uint32_t reserved_1ac;
160        uint32_t pboost;
161#define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0)
162        uint32_t reserved_1b4 [5];
163        uint32_t clkoutcfg;
164#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0)
165#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0)
166#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0)
167#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4)
168#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4)
169#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4)
170#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8)
171#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9)
172        uint32_t rstcon0;
173        uint32_t rstcon1;
174        uint32_t reserved_1d4 [2];
175        uint32_t emcdlyctl;
176#define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4)
177#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4)
178#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
179#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12)
180#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12)
181#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12)
182#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20)
183#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20)
184#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
185#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28)
186#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28)
187#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28)
188        uint32_t emccal;
189#define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7)
190#define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7)
191#define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
192#define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14)
193#define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15)
194} lpc17xx_scb;
195
196#define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000))
197
198typedef struct {
199        uint32_t reserved_00 [268435456];
200        lpc17xx_wwdt wwdt;
201        uint32_t reserved_40000020 [258040];
202        lpc17xx_scb scb;
203} lpc17xx;
204
205#define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE))
206
207#endif /* LPC17XX_REGS_H */
Note: See TracBrowser for help on using the repository browser.