1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSBSPsARMLPC24XXI2C |
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5 | */ |
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6 | |
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7 | /* |
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8 | * SPDX-License-Identifier: BSD-2-Clause |
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9 | * |
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10 | * Copyright (C) 2009, 2019 embedded brains GmbH & Co. KG |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * 1. Redistributions of source code must retain the above copyright |
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16 | * notice, this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright |
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18 | * notice, this list of conditions and the following disclaimer in the |
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19 | * documentation and/or other materials provided with the distribution. |
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20 | * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 | * POSSIBILITY OF SUCH DAMAGE. |
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32 | */ |
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33 | |
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34 | #include <bsp/i2c.h> |
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35 | #include <bsp.h> |
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36 | #include <bsp/io.h> |
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37 | #include <bsp/irq.h> |
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38 | #include <bsp/irq-generic.h> |
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39 | |
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40 | #include <rtems/score/assert.h> |
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41 | |
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42 | #include <dev/i2c/i2c.h> |
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43 | |
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44 | RTEMS_STATIC_ASSERT(I2C_M_RD == 1, lpc24xx_i2c_read_flag); |
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45 | |
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46 | typedef struct { |
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47 | i2c_bus base; |
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48 | volatile lpc24xx_i2c *regs; |
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49 | uint8_t *buf; |
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50 | const uint8_t *buf_end; |
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51 | size_t todo; |
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52 | const i2c_msg *msg; |
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53 | const i2c_msg *msg_end; |
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54 | int error; |
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55 | rtems_binary_semaphore sem; |
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56 | lpc24xx_module module; |
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57 | rtems_vector_number irq; |
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58 | } lpc24xx_i2c_bus; |
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59 | |
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60 | typedef struct { |
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61 | volatile lpc24xx_i2c *regs; |
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62 | lpc24xx_module module; |
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63 | rtems_vector_number irq; |
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64 | } lpc24xx_i2c_config; |
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65 | |
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66 | static const i2c_msg *lpc24xx_i2c_msg_inc(lpc24xx_i2c_bus *bus) |
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67 | { |
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68 | const i2c_msg *msg; |
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69 | |
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70 | msg = bus->msg + 1; |
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71 | bus->msg = msg; |
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72 | return msg; |
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73 | } |
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74 | |
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75 | static void lpc24xx_i2c_msg_inc_and_set_buf(lpc24xx_i2c_bus *bus) |
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76 | { |
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77 | const i2c_msg *msg; |
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78 | |
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79 | msg = lpc24xx_i2c_msg_inc(bus); |
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80 | bus->buf = msg->buf; |
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81 | bus->buf_end = bus->buf + msg->len; |
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82 | } |
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83 | |
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84 | static void lpc24xx_i2c_buf_inc(lpc24xx_i2c_bus *bus) |
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85 | { |
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86 | ++bus->buf; |
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87 | --bus->todo; |
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88 | } |
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89 | |
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90 | static void lpc24xx_i2c_buf_push(lpc24xx_i2c_bus *bus, uint8_t c) |
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91 | { |
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92 | while (true) { |
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93 | if (bus->buf != bus->buf_end) { |
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94 | bus->buf[0] = c; |
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95 | lpc24xx_i2c_buf_inc(bus); |
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96 | break; |
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97 | } |
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98 | |
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99 | lpc24xx_i2c_msg_inc_and_set_buf(bus); |
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100 | } |
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101 | } |
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102 | |
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103 | static uint8_t lpc24xx_i2c_buf_pop(lpc24xx_i2c_bus *bus) |
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104 | { |
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105 | while (true) { |
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106 | if (bus->buf != bus->buf_end) { |
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107 | uint8_t c; |
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108 | |
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109 | c = bus->buf[0]; |
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110 | lpc24xx_i2c_buf_inc(bus); |
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111 | return c; |
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112 | } |
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113 | |
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114 | lpc24xx_i2c_msg_inc_and_set_buf(bus); |
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115 | } |
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116 | } |
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117 | |
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118 | static void lpc24xx_i2c_setup_msg(lpc24xx_i2c_bus *bus, const i2c_msg *msg) |
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119 | { |
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120 | int can_continue; |
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121 | size_t todo; |
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122 | |
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123 | bus->msg = msg; |
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124 | bus->buf = msg->buf; |
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125 | todo = msg->len; |
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126 | bus->buf_end = bus->buf + todo; |
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127 | |
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128 | can_continue = (msg->flags & I2C_M_RD) | I2C_M_NOSTART; |
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129 | ++msg; |
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130 | |
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131 | while (msg != bus->msg_end) { |
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132 | if ((msg->flags & (I2C_M_RD | I2C_M_NOSTART)) != can_continue) { |
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133 | break; |
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134 | } |
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135 | |
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136 | todo += msg->len; |
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137 | ++msg; |
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138 | } |
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139 | |
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140 | bus->todo = todo; |
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141 | } |
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142 | |
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143 | static int lpc24xx_i2c_next_msg( |
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144 | lpc24xx_i2c_bus *bus, |
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145 | volatile lpc24xx_i2c *regs |
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146 | ) |
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147 | { |
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148 | const i2c_msg *msg; |
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149 | int error; |
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150 | |
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151 | msg = bus->msg + 1; |
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152 | error = 1; |
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153 | |
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154 | if (msg != bus->msg_end) { |
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155 | lpc24xx_i2c_setup_msg(bus, msg); |
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156 | |
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157 | if ((msg->flags & I2C_M_NOSTART) == 0) { |
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158 | regs->conset = LPC24XX_I2C_STA; |
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159 | regs->conclr = LPC24XX_I2C_SI; |
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160 | } else { |
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161 | regs->conset = LPC24XX_I2C_STO; |
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162 | regs->conclr = LPC24XX_I2C_SI; |
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163 | error = -EINVAL; |
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164 | } |
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165 | } else { |
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166 | regs->conset = LPC24XX_I2C_STO; |
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167 | regs->conclr = LPC24XX_I2C_SI; |
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168 | error = 0; |
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169 | } |
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170 | |
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171 | return error; |
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172 | } |
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173 | |
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174 | static void lpc24xx_i2c_interrupt(void *arg) |
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175 | { |
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176 | lpc24xx_i2c_bus *bus; |
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177 | volatile lpc24xx_i2c *regs; |
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178 | const i2c_msg *msg; |
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179 | int error; |
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180 | |
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181 | bus = arg; |
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182 | regs = bus->regs; |
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183 | error = 1; |
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184 | |
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185 | switch (regs->stat) { |
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186 | case 0x00: |
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187 | /* Bus error */ |
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188 | case 0x20: |
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189 | /* Slave address plus write sent, NACK received */ |
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190 | case 0x48: |
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191 | /* Slave address plus read sent, NACK received */ |
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192 | regs->conset = LPC24XX_I2C_STO | LPC24XX_I2C_AA; |
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193 | regs->conclr = LPC24XX_I2C_SI; |
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194 | error = -EIO; |
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195 | break; |
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196 | case 0x08: |
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197 | /* Start sent */ |
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198 | case 0x10: |
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199 | /* Repeated start sent */ |
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200 | msg = bus->msg; |
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201 | regs->dat = (uint8_t) ((msg->addr << 1) | (msg->flags & I2C_M_RD)); |
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202 | regs->conset = LPC24XX_I2C_AA; |
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203 | regs->conclr = LPC24XX_I2C_STA | LPC24XX_I2C_SI; |
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204 | break; |
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205 | case 0x18: |
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206 | /* Slave address plus write sent, ACK received */ |
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207 | case 0x28: |
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208 | /* Data sent, ACK received */ |
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209 | if (bus->todo > 0) { |
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210 | regs->dat = lpc24xx_i2c_buf_pop(bus); |
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211 | regs->conset = LPC24XX_I2C_AA; |
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212 | regs->conclr = LPC24XX_I2C_SI; |
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213 | } else { |
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214 | error = lpc24xx_i2c_next_msg(bus, regs); |
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215 | } |
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216 | break; |
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217 | case 0x30: |
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218 | /* Data sent, NACK received */ |
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219 | if (bus->todo == 0) { |
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220 | error = lpc24xx_i2c_next_msg(bus, regs); |
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221 | } else { |
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222 | regs->conset = LPC24XX_I2C_STO; |
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223 | regs->conclr = LPC24XX_I2C_SI; |
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224 | error = -EIO; |
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225 | } |
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226 | break; |
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227 | case 0x40: |
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228 | /* Slave address plus read sent, ACK received */ |
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229 | if (bus->todo > 1) { |
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230 | regs->conset = LPC24XX_I2C_AA; |
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231 | regs->conclr = LPC24XX_I2C_SI; |
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232 | } else { |
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233 | regs->conclr = LPC24XX_I2C_SI | LPC24XX_I2C_AA; |
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234 | } |
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235 | break; |
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236 | case 0x50: |
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237 | /* Data received, ACK returned */ |
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238 | case 0x58: |
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239 | /* Data received, NACK returned */ |
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240 | lpc24xx_i2c_buf_push(bus, regs->dat); |
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241 | |
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242 | if (bus->todo > 1) { |
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243 | regs->conset = LPC24XX_I2C_AA; |
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244 | regs->conclr = LPC24XX_I2C_SI; |
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245 | } else if (bus->todo == 1) { |
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246 | regs->conclr = LPC24XX_I2C_SI | LPC24XX_I2C_AA; |
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247 | } else { |
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248 | error = lpc24xx_i2c_next_msg(bus, regs); |
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249 | } |
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250 | break; |
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251 | case 0xF8: |
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252 | /* Do nothing */ |
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253 | break; |
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254 | default: |
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255 | error = -EIO; |
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256 | break; |
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257 | } |
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258 | |
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259 | if (error <= 0) { |
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260 | bus->error = error; |
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261 | bsp_interrupt_vector_disable(bus->irq); |
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262 | rtems_binary_semaphore_post(&bus->sem); |
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263 | } |
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264 | } |
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265 | |
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266 | static int |
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267 | lpc24xx_i2c_transfer(i2c_bus *base, i2c_msg *msgs, uint32_t msg_count) |
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268 | { |
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269 | lpc24xx_i2c_bus *bus; |
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270 | volatile lpc24xx_i2c *regs; |
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271 | uint16_t supported; |
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272 | uint32_t i; |
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273 | int eno; |
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274 | |
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275 | if (msg_count == 0){ |
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276 | return 0; |
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277 | } |
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278 | |
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279 | supported = I2C_M_RD; |
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280 | |
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281 | for (i = 0; i < msg_count; ++i) { |
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282 | if ((msgs[i].flags & ~supported) != 0) { |
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283 | return -EINVAL; |
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284 | } |
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285 | |
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286 | supported |= I2C_M_NOSTART; |
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287 | } |
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288 | |
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289 | bus = (lpc24xx_i2c_bus *) base; |
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290 | bus->msg_end = msgs + msg_count; |
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291 | lpc24xx_i2c_setup_msg(bus, msgs); |
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292 | |
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293 | regs = bus->regs; |
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294 | |
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295 | /* Start */ |
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296 | regs->conset = LPC24XX_I2C_STA; |
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297 | |
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298 | bsp_interrupt_vector_enable(bus->irq); |
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299 | eno = rtems_binary_semaphore_wait_timed_ticks( |
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300 | &bus->sem, |
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301 | bus->base.timeout |
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302 | ); |
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303 | if (eno != 0) { |
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304 | regs->conclr = LPC24XX_I2C_EN; |
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305 | regs->conset = LPC24XX_I2C_EN; |
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306 | rtems_binary_semaphore_try_wait(&bus->sem); |
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307 | return -ETIMEDOUT; |
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308 | } |
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309 | |
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310 | return bus->error; |
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311 | } |
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312 | |
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313 | /* I2C-Bus Specification and User Manual, Table 10 */ |
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314 | static const uint16_t lpc24xx_i2c_t_low_high[3][2] = { |
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315 | { 4700, 4000 }, |
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316 | { 1300, 600 }, |
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317 | { 500, 260 } |
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318 | }; |
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319 | |
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320 | static uint32_t lpc24xx_i2c_cycle_count(uint32_t scl, uint32_t x, uint32_t t) |
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321 | { |
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322 | scl = (scl * x + t - 1) / t; |
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323 | |
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324 | if (scl <= 4) { |
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325 | scl = 4; |
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326 | } else if (scl >= 0xffff) { |
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327 | scl = 0xffff; |
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328 | } |
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329 | |
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330 | return scl; |
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331 | } |
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332 | |
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333 | static int lpc24xx_i2c_set_clock(i2c_bus *base, unsigned long clock) |
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334 | { |
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335 | lpc24xx_i2c_bus *bus; |
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336 | volatile lpc24xx_i2c *regs; |
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337 | size_t i; |
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338 | uint32_t low; |
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339 | uint32_t high; |
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340 | uint32_t t; |
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341 | uint32_t scl; |
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342 | |
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343 | if (clock <= 100000) { |
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344 | i = 0; |
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345 | } else if (clock <= 400000) { |
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346 | i = 1; |
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347 | } else { |
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348 | i = 2; |
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349 | } |
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350 | |
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351 | low = lpc24xx_i2c_t_low_high[i][0]; |
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352 | high = lpc24xx_i2c_t_low_high[i][1]; |
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353 | t = low + high; |
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354 | scl = (LPC24XX_PCLK + clock - 1) / clock; |
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355 | |
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356 | bus = (lpc24xx_i2c_bus *) base; |
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357 | regs = bus->regs; |
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358 | |
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359 | regs->scll = lpc24xx_i2c_cycle_count(scl, low, t); |
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360 | regs->sclh = lpc24xx_i2c_cycle_count(scl, high, t); |
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361 | |
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362 | return 0; |
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363 | } |
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364 | |
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365 | static void |
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366 | lpc24xx_i2c_destroy(i2c_bus *base) |
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367 | { |
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368 | lpc24xx_i2c_bus *bus; |
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369 | rtems_status_code sc; |
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370 | |
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371 | bus = (lpc24xx_i2c_bus *) base; |
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372 | |
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373 | sc = rtems_interrupt_handler_remove(bus->irq, lpc24xx_i2c_interrupt, bus); |
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374 | _Assert(sc == RTEMS_SUCCESSFUL); |
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375 | (void) sc; |
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376 | |
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377 | /* Disable I2C module */ |
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378 | bus->regs->conclr = LPC24XX_I2C_EN; |
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379 | |
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380 | sc = lpc24xx_module_disable(bus->module); |
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381 | _Assert(sc == RTEMS_SUCCESSFUL); |
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382 | (void) sc; |
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383 | |
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384 | rtems_binary_semaphore_destroy(&bus->sem); |
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385 | i2c_bus_destroy_and_free(&bus->base); |
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386 | } |
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387 | |
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388 | static int lpc24xx_i2c_init(lpc24xx_i2c_bus *bus) |
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389 | { |
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390 | rtems_status_code sc; |
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391 | |
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392 | sc = lpc24xx_module_enable(bus->module, LPC24XX_MODULE_PCLK_DEFAULT); |
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393 | _Assert(sc == RTEMS_SUCCESSFUL); |
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394 | (void) sc; |
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395 | |
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396 | /* Disable I2C module */ |
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397 | bus->regs->conclr = LPC24XX_I2C_EN; |
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398 | |
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399 | sc = rtems_interrupt_handler_install( |
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400 | bus->irq, |
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401 | "I2C", |
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402 | RTEMS_INTERRUPT_UNIQUE, |
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403 | lpc24xx_i2c_interrupt, |
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404 | bus |
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405 | ); |
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406 | if (sc != RTEMS_SUCCESSFUL) { |
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407 | return EAGAIN; |
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408 | } |
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409 | |
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410 | rtems_binary_semaphore_init(&bus->sem, "I2C"); |
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411 | |
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412 | lpc24xx_i2c_set_clock(&bus->base, I2C_BUS_CLOCK_DEFAULT); |
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413 | |
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414 | /* Initialize I2C module */ |
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415 | bus->regs->conset = LPC24XX_I2C_EN; |
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416 | |
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417 | return 0; |
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418 | } |
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419 | |
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420 | static int i2c_bus_register_lpc24xx( |
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421 | const char *bus_path, |
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422 | const lpc24xx_i2c_config *config |
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423 | ) |
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424 | { |
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425 | lpc24xx_i2c_bus *bus; |
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426 | int eno; |
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427 | |
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428 | bus = (lpc24xx_i2c_bus *) i2c_bus_alloc_and_init(sizeof(*bus)); |
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429 | if (bus == NULL){ |
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430 | return -1; |
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431 | } |
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432 | |
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433 | bus->regs = config->regs; |
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434 | bus->module = config->module; |
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435 | bus->irq = config->irq; |
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436 | |
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437 | eno = lpc24xx_i2c_init(bus); |
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438 | if (eno != 0) { |
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439 | (*bus->base.destroy)(&bus->base); |
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440 | rtems_set_errno_and_return_minus_one(eno); |
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441 | } |
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442 | |
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443 | bus->base.transfer = lpc24xx_i2c_transfer; |
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444 | bus->base.set_clock = lpc24xx_i2c_set_clock; |
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445 | bus->base.destroy = lpc24xx_i2c_destroy; |
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446 | |
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447 | return i2c_bus_register(&bus->base, bus_path); |
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448 | } |
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449 | |
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450 | int lpc24xx_register_i2c_0(void) |
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451 | { |
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452 | static const lpc24xx_i2c_config config = { |
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453 | .regs = (volatile lpc24xx_i2c *) I2C0_BASE_ADDR, |
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454 | .module = LPC24XX_MODULE_I2C_0, |
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455 | .irq = LPC24XX_IRQ_I2C_0 |
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456 | }; |
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457 | |
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458 | return i2c_bus_register_lpc24xx( |
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459 | LPC24XX_I2C_0_BUS_PATH, |
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460 | &config |
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461 | ); |
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462 | } |
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463 | |
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464 | int lpc24xx_register_i2c_1(void) |
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465 | { |
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466 | static const lpc24xx_i2c_config config = { |
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467 | .regs = (volatile lpc24xx_i2c *) I2C1_BASE_ADDR, |
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468 | .module = LPC24XX_MODULE_I2C_1, |
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469 | .irq = LPC24XX_IRQ_I2C_1 |
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470 | }; |
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471 | |
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472 | return i2c_bus_register_lpc24xx( |
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473 | LPC24XX_I2C_2_BUS_PATH, |
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474 | &config |
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475 | ); |
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476 | } |
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477 | |
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478 | int lpc24xx_register_i2c_2(void) |
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479 | { |
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480 | static const lpc24xx_i2c_config config = { |
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481 | .regs = (volatile lpc24xx_i2c *) I2C2_BASE_ADDR, |
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482 | .module = LPC24XX_MODULE_I2C_2, |
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483 | .irq = LPC24XX_IRQ_I2C_2 |
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484 | }; |
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485 | |
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486 | return i2c_bus_register_lpc24xx( |
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487 | LPC24XX_I2C_2_BUS_PATH, |
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488 | &config |
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489 | ); |
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490 | } |
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