source: rtems/bsps/arm/lpc176x/include/bsp/gpio-defs.h @ c77cd426

5
Last change on this file since c77cd426 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 6.9 KB
Line 
1/**
2 * @file gpio-defs.h
3 *
4 * @ingroup lpc176x
5 *
6 * @brief API definitions of the GPIO driver for the lpc176x bsp in RTEMS.
7 */
8
9/*
10 * Copyright (c) 2014 Taller Technologies.
11 *
12 * @author  Boretto Martin    (martin.boretto@tallertechnologies.com)
13 * @author  Diaz Marcos (marcos.diaz@tallertechnologies.com)
14 * @author  Lenarduzzi Federico  (federico.lenarduzzi@tallertechnologies.com)
15 * @author  Daniel Chicco  (daniel.chicco@tallertechnologies.com)
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.org/license/LICENSE.
20 */
21
22#ifndef LIBBSP_ARM_LPC176X_GPIO_DEFS_H
23#define LIBBSP_ARM_LPC176X_GPIO_DEFS_H
24
25#include <bsp/common-types.h>
26
27#ifdef __cplusplus
28extern "C" {
29#endif /* __cplusplus */
30
31/* General Purpose Input/Output (GPIO) */
32#define LPC176X_GPIO_BASE_ADDR 0x40028000U
33#define LPC176X_GPIO_INTERRUPT_STATUS 0x40028080U
34
35#define LPC176X_IOPIN0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
36                                                  0x00U ) )
37#define LPC176X_IOSET0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
38                                                  0x04U ) )
39#define LPC176X_IODIR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
40                                                  0x08U ) )
41#define LPC176X_IOCLR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
42                                                  0x0CU ) )
43#define LPC176X_IOPIN1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
44                                                  0x10U ) )
45#define LPC176X_IOSET1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
46                                                  0x14U ) )
47#define LPC176X_IODIR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
48                                                  0x18U ) )
49#define LPC176X_IOCLR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
50                                                  0x1CU ) )
51
52/* GPIO Interrupt Registers */
53#define LPC176X_IO0_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
54                                                        + 0x90U ) )
55#define LPC176X_IO0_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
56                                                        + 0x94U ) )
57#define LPC176X_IO0_INT_STAT_R ( *(volatile uint32_t *) ( \
58                                   LPC176X_GPIO_BASE_ADDR \
59                                   + 0x84U ) )
60#define LPC176X_IO0_INT_STAT_F ( *(volatile uint32_t *) ( \
61                                   LPC176X_GPIO_BASE_ADDR \
62                                   + 0x88U ) )
63#define LPC176X_IO0_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
64                                                       + 0x8CU ) )
65#define LPC176X_IO2_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
66                                                        + 0xB0U ) )
67#define LPC176X_IO2_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
68                                                        + 0xB4U ) )
69#define LPC176X_IO2_INT_STAT_R ( *(volatile uint32_t *) ( \
70                                   LPC176X_GPIO_BASE_ADDR \
71                                   + 0xA4U ) )
72#define LPC176X_IO2_INT_STAT_F ( *(volatile uint32_t *) ( \
73                                   LPC176X_GPIO_BASE_ADDR \
74                                   + 0xA8U ) )
75#define LPC176X_IO2_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
76                                                       + 0xACU ) )
77#define LPC176X_IO_INT_STAT ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
78                                                       + 0x80U ) )
79
80#define LPC176X_RESERVED_ISR_FUNCT_SIZE 2U
81#define LPC176X_RESERVED_ISR_FUNCT_MAX_SIZE 5U
82
83#define LPC176X_MAX_PORT_NUMBER 160U
84#define LPC176X_SET_BIT( reg, pin, value ) \
85  reg = ( reg & ~( 1U << pin ) ) | ( ( value & 1U ) << pin )
86
87#define LPC176X_INT_STATUS ( *(volatile uint32_t *) \
88                             ( LPC176X_GPIO_INTERRUPT_STATUS ) )
89#define LPC176X_INT_STATUS_P0 1U
90#define LPC176X_INT_STATUS_P2 ( 1U << 2U )
91#define LPC176X_INT_ENABLE 1U
92#define LPC176X_INT_DISABLE 0U
93
94#define LPC176X_IRQ_EINT_3 21U
95
96#define LPC176X_PIN_BIT( pin ) ( 1U << pin )
97
98/**
99 * @brief The direction of the GPIO port (input or output).
100 *
101 * Enumerated type to define the set of function types for a gpio device.
102 */
103typedef enum {
104  LPC176X_GPIO_FUNCTION_INPUT,
105  LPC176X_GPIO_FUNCTION_OUTPUT,
106  LPC176X_GPIO_FUNCTION_COUNT
107}
108lpc176x_gpio_direction;
109
110/**
111 * @brief The interrupt sources edge for a GPIO.
112 *
113 * Enumerated type to define the set of interrupt types for a gpio device.
114 */
115typedef enum {
116  LPC176X_GPIO_INTERRUPT_DISABLE,
117  LPC176X_GPIO_INTERRUPT_RISING,
118  LPC176X_GPIO_INTERRUPT_FALLING,
119  LPC176X_GPIO_INTERRUPT_BOTH,
120  LPC176X_GPIO_INTERRUPT_COUNT
121} lpc176x_gpio_interrupt;
122
123/**
124 * @brief The ports for a GPIO.
125 *
126 * Enumerated type to define the set of ports for a gpio device.
127 */
128typedef enum {
129  LPC176X_GPIO_PORT_0,
130  LPC176X_GPIO_PORT_1,
131  LPC176X_GPIO_PORT_2,
132  LPC176X_GPIO_PORT_3,
133  LPC176X_GPIO_PORT_4,
134  LPC176X_GPIO_PORTS_COUNT
135} lpc176x_gpio_ports;
136
137/**
138 * @brief Addresses for a GPIO.
139 *
140 * Enumerated type to define the set of fio bases addresses
141 *     for a gpio device.
142 */
143typedef enum {
144  LPC176X_FIO0_BASE_ADDRESS = 0x2009C000U,
145  LPC176X_FIO1_BASE_ADDRESS = 0x2009C020U,
146  LPC176X_FIO2_BASE_ADDRESS = 0x2009C040U,
147  LPC176X_FIO3_BASE_ADDRESS = 0x2009C060U,
148  LPC176X_FIO4_BASE_ADDRESS = 0x2009C080U,
149} lpc176x_gpio_address;
150
151/**
152 * @brief Addresses for the two interrupts.
153 *
154 * Enumerated type to define the set of interrupt addresses
155 *     for a gpio device.
156 */
157typedef enum {
158  LPC176X_IO0_INT_BASE_ADDRESS = 0x40028084U,
159  LPC176X_IO2_INT_BASE_ADDRESS = 0x400280A4U,
160} lpc176x_interrupt_address;
161
162/**
163 * @brief GPIO Interrupt register map.
164 */
165typedef struct {
166  /**
167   * @brief Interrupt Enable for Rising edge.
168   */
169  volatile uint32_t StatR;
170  /**
171   * @brief Interrupt Enable for Falling edge.
172   */
173  volatile uint32_t StatF;
174  /**
175   * @brief Interrupt Clear.
176   */
177  volatile uint32_t Clr;
178  /**
179   * @brief Interrupt Enable for Rising edge.
180   */
181  volatile uint32_t EnR;
182  /**
183   * @brief Interrupt Enable for Falling edge.
184   */
185  volatile uint32_t EnF;
186} lpc176x_interrupt_control;
187
188/**
189 * @brief A function that attends an interrupt for GPIO.
190 *
191 * @param  pin Pin number.
192 * @param edge Interrupt.
193 * @return Pointer to the interrupt function.
194 */
195typedef void (*lpc176x_gpio_interrupt_function) (
196  const lpc176x_pin_number     pin,
197  const lpc176x_gpio_interrupt edge
198);
199
200/**
201 * @brief A registered interrupt function for the pin 'pin'.
202 */
203typedef struct {
204  /**
205   * @brief Pin board.
206   */
207  lpc176x_pin_number pin;
208  /**
209   * @brief A function that attends an interrupt for 'pin'.
210   */
211  lpc176x_gpio_interrupt_function function;
212} lpc176x_registered_interrupt_function;
213
214#ifdef __cplusplus
215}
216#endif /* __cplusplus */
217
218#endif /* LIBBSP_ARM_LPC176X_GPIO_DEFS_H */
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