1 | /** |
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2 | * @file can-defs.h |
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3 | * |
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4 | * @ingroup lpc176x |
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5 | * |
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6 | * @brief CAN controller for the lpc176x controller. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2014 Taller Technologies. |
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11 | * |
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12 | * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) |
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13 | * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) |
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14 | * |
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15 | * The license and distribution terms for this file may be |
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16 | * found in the file LICENSE in this distribution or at |
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17 | * http://www.rtems.org/license/LICENSE. |
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18 | */ |
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19 | |
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20 | #ifndef LPC176X_TIMER_DEFS_H |
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21 | #define LPC176X_TIMER_DEFS_H |
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22 | |
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23 | #include <bsp/common-types.h> |
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24 | #include <bsp/can.h> |
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25 | |
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26 | /* CAN ACCEPTANCE FILTER */ |
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27 | #define CAN_ACCEPT_BASE_ADDR 0x4003C000 |
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28 | |
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29 | #define CAN_DRIVER_IS_MINOR_VALID( minor ) ( minor < CAN_DEVICES_NUMBER ) |
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30 | #define CAN_DEFAULT_BAUD_RATE 1000000u |
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31 | #define CAN_DEFAULT_INTERRUPT_CONFIGURATION 0 |
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32 | |
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33 | #define MAX_NUMBER_OF_CAN_BITS 25u |
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34 | #define MIN_NUMBER_OF_CAN_BITS 4u |
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35 | #define CAN_BRP_EXTRA_BIT 1u |
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36 | #define CAN_TSEG_EXTRA_BITS 3u |
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37 | #define MAX_TSEG1_TSEG2_BITS 22u |
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38 | |
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39 | #define CAN_GSR_RBS_MASK 1u |
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40 | #define CAN_CMR_RRB_MASK 4u |
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41 | |
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42 | #define CAN_MAXIMUM_DATA_SIZE 8u |
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43 | #define CAN10_MAXIMUM_ID 0x7FFu |
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44 | |
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45 | /** |
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46 | * @brief The Time segments of a CAN bit. |
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47 | */ |
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48 | typedef enum { |
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49 | CAN_TSEG1, |
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50 | CAN_TSEG2, |
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51 | CAN_NUMBER_OF_TSEG, |
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52 | } can_tseg_number; |
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53 | |
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54 | #define CAN_BTR_TSEG1_SHIFT 16u |
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55 | #define CAN_BTR_TSEG2_SHIFT 20u |
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56 | #define CAN_BTR_SJW_SHIFT 14u |
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57 | #define CAN_BTR_BRP_SHIFT 0u |
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58 | |
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59 | #define CAN_BTR_TSEG1_MASK 0x000F0000U |
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60 | #define CAN_BTR_TSEG2_MASK 0x00700000U |
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61 | #define CAN_BTR_SJW_MASK 0x0000C000U |
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62 | #define CAN_BTR_BRP_MASK 0x000003FFU |
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63 | |
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64 | #define WRONG_BTR_VALUE 0xFFFFFFFF |
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65 | |
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66 | /** |
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67 | * @brief The transmit buffers of the CAN device. |
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68 | */ |
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69 | typedef enum { |
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70 | CAN_TRANSMIT1, |
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71 | CAN_TRANSMIT2, |
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72 | CAN_TRANSMIT3, |
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73 | CAN_NUMBER_OF_TRANSMIT_BUFFERS |
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74 | } can_transmit_number; |
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75 | |
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76 | /** |
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77 | * @brief The CAN status and control masks to send a message |
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78 | * for each transmit buffer. |
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79 | */ |
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80 | typedef struct { |
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81 | uint32_t can_status_mask; |
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82 | uint32_t not_cc_cmr_value; |
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83 | } can_transmit_info; |
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84 | |
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85 | /** @brief Represents the CAN controller registers.*/ |
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86 | typedef struct { |
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87 | volatile uint32_t MOD; |
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88 | volatile uint32_t CMR; |
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89 | volatile uint32_t GSR; |
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90 | volatile uint32_t ICR; |
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91 | volatile uint32_t IER; |
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92 | volatile uint32_t BTR; |
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93 | volatile uint32_t EWL; |
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94 | volatile uint32_t SR; |
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95 | volatile registers_can_message receive; |
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96 | volatile registers_can_message transmit[ CAN_NUMBER_OF_TRANSMIT_BUFFERS ]; |
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97 | } can_device; |
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98 | |
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99 | /** |
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100 | * @brief A TX or RX pin for each CAN device . |
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101 | */ |
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102 | typedef enum { |
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103 | CAN_TX_PIN, |
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104 | CAN_RX_PIN, |
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105 | NUMBER_OF_CAN_PINS |
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106 | } can_pin_number; |
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107 | |
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108 | /** |
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109 | * @brief A driver entry for each low level device. |
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110 | */ |
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111 | typedef struct { |
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112 | can_device *const device; |
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113 | const lpc176x_module module; |
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114 | const uint32_t pconp_pin; |
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115 | const uint32_t pins[ NUMBER_OF_CAN_PINS ]; |
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116 | const lpc176x_pin_function pinfunction; |
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117 | } can_driver_entry; |
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118 | |
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119 | /** @brief Represents the CAN centralized registers. */ |
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120 | typedef struct { |
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121 | volatile uint32_t TX_SR; |
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122 | volatile uint32_t RX_SR; |
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123 | volatile uint32_t MSR; |
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124 | } can_central; |
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125 | |
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126 | /** @brief Represents the acceptance filter registers. */ |
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127 | typedef struct { |
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128 | volatile uint32_t AFMR; |
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129 | volatile uint32_t SFF_SA; |
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130 | volatile uint32_t SFF_GRP_SA; |
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131 | volatile uint32_t EFF_SA; |
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132 | volatile uint32_t EFF_GRP_SA; |
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133 | volatile uint32_t EOT; |
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134 | volatile uint32_t LUT_ERR_ADR; |
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135 | volatile uint32_t LUT_ERR; |
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136 | volatile uint32_t FCANIE; |
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137 | volatile uint32_t FCANIC0; |
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138 | volatile uint32_t FCANIC1; |
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139 | } can_acceptance_filter; |
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140 | |
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141 | /** |
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142 | * @brief The possible CAN formats for a message. |
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143 | */ |
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144 | typedef enum { |
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145 | CANStandard = 0, |
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146 | CANExtended = 1, |
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147 | CANAny = 2 |
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148 | } can_format; |
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149 | |
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150 | /** |
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151 | * @brief The types of message. |
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152 | */ |
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153 | typedef enum { |
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154 | CANData = 0, |
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155 | CANRemote = 1 |
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156 | } can_type; |
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157 | |
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158 | #define CAN_INTERRUPT_TYPE_MASK 0x1ffu |
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159 | |
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160 | /** |
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161 | * @brief The vector with all the callbacks for the CAN isr. |
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162 | */ |
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163 | typedef lpc176x_can_isr lpc176x_can_isr_vector[ CAN_IRQ_NUMBER ]; |
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164 | |
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165 | #define CAN_MOD_RM 0x00000001U |
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166 | |
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167 | #define CAN_ACCF_AFMR_ACCOF 0x00000001U |
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168 | #define CAN_ACCF_AFMR_ACCBP 0x00000002U |
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169 | #define CAN_ACCF_AFMR_EFCAN 0x00000004U |
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170 | |
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171 | #define CAN_IER_RIE 0x000000001U |
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172 | #define CAN_IER_TIE1 0x000000002U |
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173 | #define CAN_IER_EIE 0x000000004U |
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174 | #define CAN_IER_DOIE 0x000000008U |
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175 | #define CAN_IER_WUIE 0x000000010U |
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176 | #define CAN_IER_EPIEX 0x000000020U |
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177 | #define CAN_IER_ALIEX 0x000000040U |
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178 | #define CAN_IER_BEIEX 0x000000080U |
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179 | #define CAN_IER_IDIEX 0x000000100U |
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180 | #define CAN_IER_TIE2 0x000000200U |
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181 | #define CAN_IER_TIE3 0x000000400U |
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182 | |
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183 | #endif /*LPC176X_TIMER_DEFS_H*/ |
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