source: rtems/bsps/arm/lm3s69xx/start/syscon.c @ e0dd8a5a

5
Last change on this file since e0dd8a5a was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org>
3 *
4 * The license and distribution terms for this file may be
5 * found in the file LICENSE in this distribution or at
6 * http://www.rtems.org/license/LICENSE.
7 */
8
9#include <bsp/syscon.h>
10#include <bsp/lm3s69xx.h>
11#include <rtems.h>
12
13static void delay_3_clocks(void)
14{
15  asm volatile(
16      "nop\n\t"
17      "nop\n\t"
18      "nop");
19}
20
21void __attribute__((naked)) lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count)
22{
23    asm volatile(
24                 "subs  r0, #1\n\t"
25                 "bne   lm3s69xx_syscon_delay_3x_clocks\n\t"
26                 "bx    lr"
27                 );
28}
29
30void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable)
31{
32  volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
33  uint32_t mask = 1 << port;
34  rtems_interrupt_level level;
35
36  rtems_interrupt_disable(level);
37
38  if (enable)
39    syscon->rcgc2 |= mask;
40  else
41    syscon->rcgc2 &= ~mask;
42
43  delay_3_clocks();
44
45  rtems_interrupt_enable(level);
46}
47
48void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable)
49{
50  volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
51  uint32_t mask = 1 << port;
52  rtems_interrupt_level level;
53
54  rtems_interrupt_disable(level);
55
56  if (enable)
57    syscon->rcgc1 |= mask;
58  else
59    syscon->rcgc1 &= ~mask;
60
61  delay_3_clocks();
62
63  rtems_interrupt_enable(level);
64}
65
66void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable)
67{
68  volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
69  uint32_t mask = 1 << (port + 4);
70  rtems_interrupt_level level;
71
72  rtems_interrupt_disable(level);
73
74  if (enable)
75    syscon->rcgc1 |= mask;
76  else
77    syscon->rcgc1 &= ~mask;
78
79  delay_3_clocks();
80
81  rtems_interrupt_enable(level);
82}
83
84void lm3s69xx_syscon_enable_pwm_clock(bool enable)
85{
86  volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
87  rtems_interrupt_level level;
88
89  rtems_interrupt_disable(level);
90
91  if (enable)
92    syscon->rcgc0 |= SYSCONRCGC0_PWM;
93  else
94    syscon->rcgc0 &= ~SYSCONRCGC0_PWM;
95
96  delay_3_clocks();
97
98  rtems_interrupt_enable(level);
99}
100
101/**
102 * Sets PWMDIV field in the RCC register.
103 *
104 * @note div should be one of SCRCC_PWMDIV_DIV?_VAL constants.
105 */
106void lm3s69xx_syscon_set_pwmdiv(unsigned int div)
107{
108  volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
109  rtems_interrupt_level level;
110
111  rtems_interrupt_disable(level);
112  syscon->rcc = (syscon->rcc & ~SYSCONRCC_PWMDIV_MSK) | SYSCONRCC_PWMDIV(div)
113      | SYSCONRCC_USEPWMDIV;
114  rtems_interrupt_enable(level);
115}
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