[f22bba3] | 1 | /* |
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| 2 | * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> |
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| 3 | * |
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| 4 | * The license and distribution terms for this file may be |
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| 5 | * found in the file LICENSE in this distribution or at |
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[c499856] | 6 | * http://www.rtems.org/license/LICENSE. |
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[f22bba3] | 7 | */ |
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| 8 | |
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| 9 | #include <bsp/syscon.h> |
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| 10 | #include <bsp/lm3s69xx.h> |
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| 11 | #include <rtems.h> |
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| 12 | |
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| 13 | static void delay_3_clocks(void) |
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| 14 | { |
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| 15 | asm volatile( |
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| 16 | "nop\n\t" |
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| 17 | "nop\n\t" |
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| 18 | "nop"); |
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| 19 | } |
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| 20 | |
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[0c47440] | 21 | void __attribute__((naked)) lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count) |
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| 22 | { |
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| 23 | asm volatile( |
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| 24 | "subs r0, #1\n\t" |
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| 25 | "bne lm3s69xx_syscon_delay_3x_clocks\n\t" |
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| 26 | "bx lr" |
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| 27 | ); |
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| 28 | } |
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| 29 | |
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[f22bba3] | 30 | void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable) |
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| 31 | { |
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| 32 | volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; |
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| 33 | uint32_t mask = 1 << port; |
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| 34 | rtems_interrupt_level level; |
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| 35 | |
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| 36 | rtems_interrupt_disable(level); |
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| 37 | |
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| 38 | if (enable) |
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| 39 | syscon->rcgc2 |= mask; |
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| 40 | else |
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| 41 | syscon->rcgc2 &= ~mask; |
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| 42 | |
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| 43 | delay_3_clocks(); |
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| 44 | |
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| 45 | rtems_interrupt_enable(level); |
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| 46 | } |
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| 47 | |
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| 48 | void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable) |
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| 49 | { |
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| 50 | volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; |
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| 51 | uint32_t mask = 1 << port; |
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| 52 | rtems_interrupt_level level; |
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| 53 | |
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| 54 | rtems_interrupt_disable(level); |
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| 55 | |
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| 56 | if (enable) |
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| 57 | syscon->rcgc1 |= mask; |
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| 58 | else |
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| 59 | syscon->rcgc1 &= ~mask; |
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| 60 | |
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| 61 | delay_3_clocks(); |
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| 62 | |
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| 63 | rtems_interrupt_enable(level); |
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| 64 | } |
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| 65 | |
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| 66 | void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable) |
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| 67 | { |
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| 68 | volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; |
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| 69 | uint32_t mask = 1 << (port + 4); |
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| 70 | rtems_interrupt_level level; |
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| 71 | |
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| 72 | rtems_interrupt_disable(level); |
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| 73 | |
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| 74 | if (enable) |
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| 75 | syscon->rcgc1 |= mask; |
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| 76 | else |
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| 77 | syscon->rcgc1 &= ~mask; |
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| 78 | |
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| 79 | delay_3_clocks(); |
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| 80 | |
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| 81 | rtems_interrupt_enable(level); |
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| 82 | } |
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| 83 | |
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| 84 | void lm3s69xx_syscon_enable_pwm_clock(bool enable) |
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| 85 | { |
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| 86 | volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; |
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| 87 | rtems_interrupt_level level; |
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| 88 | |
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| 89 | rtems_interrupt_disable(level); |
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| 90 | |
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| 91 | if (enable) |
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| 92 | syscon->rcgc0 |= SYSCONRCGC0_PWM; |
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| 93 | else |
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| 94 | syscon->rcgc0 &= ~SYSCONRCGC0_PWM; |
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| 95 | |
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| 96 | delay_3_clocks(); |
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| 97 | |
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| 98 | rtems_interrupt_enable(level); |
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| 99 | } |
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| 100 | |
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| 101 | /** |
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| 102 | * Sets PWMDIV field in the RCC register. |
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| 103 | * |
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| 104 | * @note div should be one of SCRCC_PWMDIV_DIV?_VAL constants. |
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| 105 | */ |
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| 106 | void lm3s69xx_syscon_set_pwmdiv(unsigned int div) |
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| 107 | { |
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| 108 | volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON; |
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| 109 | rtems_interrupt_level level; |
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| 110 | |
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| 111 | rtems_interrupt_disable(level); |
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| 112 | syscon->rcc = (syscon->rcc & ~SYSCONRCC_PWMDIV_MSK) | SYSCONRCC_PWMDIV(div) |
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| 113 | | SYSCONRCC_USEPWMDIV; |
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| 114 | rtems_interrupt_enable(level); |
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| 115 | } |
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