| 1 | /** |
|---|
| 2 | * @file |
|---|
| 3 | * |
|---|
| 4 | * @ingroup lm3s69xx_reg |
|---|
| 5 | * |
|---|
| 6 | * @brief Register definitions. |
|---|
| 7 | */ |
|---|
| 8 | |
|---|
| 9 | /* |
|---|
| 10 | * Copyright (c) 2013 Eugeniy Meshcheryakov <eugen@debian.org> |
|---|
| 11 | * |
|---|
| 12 | * Copyright (c) 2011 Sebastian Huber. All rights reserved. |
|---|
| 13 | * |
|---|
| 14 | * embedded brains GmbH |
|---|
| 15 | * Obere Lagerstr. 30 |
|---|
| 16 | * 82178 Puchheim |
|---|
| 17 | * Germany |
|---|
| 18 | * <rtems@embedded-brains.de> |
|---|
| 19 | * |
|---|
| 20 | * The license and distribution terms for this file may be |
|---|
| 21 | * found in the file LICENSE in this distribution or at |
|---|
| 22 | * http://www.rtems.org/license/LICENSE. |
|---|
| 23 | */ |
|---|
| 24 | |
|---|
| 25 | #ifndef LIBBSP_ARM_LM3S69XX_LM3S69XX_H |
|---|
| 26 | #define LIBBSP_ARM_LM3S69XX_LM3S69XX_H |
|---|
| 27 | #include <bspopts.h> |
|---|
| 28 | #include <bsp/utility.h> |
|---|
| 29 | |
|---|
| 30 | /** |
|---|
| 31 | * @defgroup lm3s69xx_reg Register Definitions |
|---|
| 32 | * |
|---|
| 33 | * @ingroup RTEMSBSPsARMLM3S69XX |
|---|
| 34 | * |
|---|
| 35 | * @brief Register Definitions |
|---|
| 36 | */ |
|---|
| 37 | |
|---|
| 38 | #define LM3S69XX_SYSCON_BASE 0x400fe000 |
|---|
| 39 | |
|---|
| 40 | #define LM3S69XX_UART_0_BASE 0x4000c000 |
|---|
| 41 | #define LM3S69XX_UART_1_BASE 0x4000d000 |
|---|
| 42 | #define LM3S69XX_UART_2_BASE 0x4000e000 |
|---|
| 43 | |
|---|
| 44 | #ifdef LM3S69XX_USE_AHB_FOR_GPIO |
|---|
| 45 | #define LM3S69XX_GPIO_A_BASE 0x40058000 |
|---|
| 46 | #define LM3S69XX_GPIO_B_BASE 0x40059000 |
|---|
| 47 | #define LM3S69XX_GPIO_C_BASE 0x4005a000 |
|---|
| 48 | #define LM3S69XX_GPIO_D_BASE 0x4005b000 |
|---|
| 49 | #define LM3S69XX_GPIO_E_BASE 0x4005c000 |
|---|
| 50 | #define LM3S69XX_GPIO_F_BASE 0x4005d000 |
|---|
| 51 | #if LM3S69XX_NUM_GPIO_BLOCKS > 6 |
|---|
| 52 | #define LM3S69XX_GPIO_G_BASE 0x4005e000 |
|---|
| 53 | #if LM3S69XX_NUM_GPIO_BLOCKS > 7 |
|---|
| 54 | #define LM3S69XX_GPIO_H_BASE 0x4005f000 |
|---|
| 55 | #endif |
|---|
| 56 | #endif |
|---|
| 57 | |
|---|
| 58 | #define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(LM3S69XX_GPIO_A_BASE + (port) * 0x1000)) |
|---|
| 59 | #else /* LM3S69XX_USE_AHB_FOR_GPIO */ |
|---|
| 60 | #define LM3S69XX_GPIO_A_BASE 0x40004000 |
|---|
| 61 | #define LM3S69XX_GPIO_B_BASE 0x40005000 |
|---|
| 62 | #define LM3S69XX_GPIO_C_BASE 0x40006000 |
|---|
| 63 | #define LM3S69XX_GPIO_D_BASE 0x40007000 |
|---|
| 64 | #define LM3S69XX_GPIO_E_BASE 0x40024000 |
|---|
| 65 | #define LM3S69XX_GPIO_F_BASE 0x40025000 |
|---|
| 66 | #if LM3S69XX_NUM_GPIO_BLOCKS > 6 |
|---|
| 67 | #define LM3S69XX_GPIO_G_BASE 0x40026000 |
|---|
| 68 | #if LM3S69XX_NUM_GPIO_BLOCKS > 7 |
|---|
| 69 | #define LM3S69XX_GPIO_H_BASE 0x40027000 |
|---|
| 70 | #endif |
|---|
| 71 | #endif |
|---|
| 72 | |
|---|
| 73 | #define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(((port) < 4) ? \ |
|---|
| 74 | (LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \ |
|---|
| 75 | (LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000))) |
|---|
| 76 | #endif /* LM3S69XX_USE_AHB_FOR_GPIO */ |
|---|
| 77 | |
|---|
| 78 | #define LM3S69XX_SSI_0_BASE 0x40008000 |
|---|
| 79 | #if LM3S69XX_NUM_SSI_BLOCKS > 1 |
|---|
| 80 | #define LM3S69XX_SSI_1_BASE 0x40009000 |
|---|
| 81 | #if LM3S69XX_NUM_SSI_BLOCKS > 2 |
|---|
| 82 | #define LM3S69XX_SSI_2_BASE 0x4000A000 |
|---|
| 83 | #if LM3S69XX_NUM_SSI_BLOCKS > 3 |
|---|
| 84 | #define LM3S69XX_SSI_3_BASE 0x4000B000 |
|---|
| 85 | #endif |
|---|
| 86 | #endif |
|---|
| 87 | #endif |
|---|
| 88 | |
|---|
| 89 | #define LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE) |
|---|
| 90 | |
|---|
| 91 | #define LM3S69XX_PLL_FREQUENCY 400000000U |
|---|
| 92 | |
|---|
| 93 | typedef struct { |
|---|
| 94 | uint32_t data[256]; /* Masked data registers are included here. */ |
|---|
| 95 | uint32_t dir; |
|---|
| 96 | uint32_t is; |
|---|
| 97 | uint32_t ibe; |
|---|
| 98 | uint32_t iev; |
|---|
| 99 | uint32_t im; |
|---|
| 100 | uint32_t ris; |
|---|
| 101 | uint32_t mis; |
|---|
| 102 | uint32_t icr; |
|---|
| 103 | uint32_t afsel; |
|---|
| 104 | |
|---|
| 105 | uint32_t reserved_0[55]; |
|---|
| 106 | |
|---|
| 107 | uint32_t dr2r; |
|---|
| 108 | uint32_t dr4r; |
|---|
| 109 | uint32_t dr8r; |
|---|
| 110 | uint32_t odr; |
|---|
| 111 | uint32_t pur; |
|---|
| 112 | uint32_t pdr; |
|---|
| 113 | uint32_t slr; |
|---|
| 114 | uint32_t den; |
|---|
| 115 | uint32_t lock; |
|---|
| 116 | uint32_t cr; |
|---|
| 117 | uint32_t amsel; |
|---|
| 118 | } lm3s69xx_gpio; |
|---|
| 119 | |
|---|
| 120 | typedef struct { |
|---|
| 121 | uint32_t did0; |
|---|
| 122 | uint32_t did1; |
|---|
| 123 | |
|---|
| 124 | uint32_t dc0; |
|---|
| 125 | uint32_t reserved_0; |
|---|
| 126 | uint32_t dc1; |
|---|
| 127 | uint32_t dc2; |
|---|
| 128 | uint32_t dc3; |
|---|
| 129 | uint32_t dc4; |
|---|
| 130 | uint32_t dc5; |
|---|
| 131 | uint32_t dc6; |
|---|
| 132 | uint32_t dc7; |
|---|
| 133 | |
|---|
| 134 | uint32_t reserved_1; |
|---|
| 135 | |
|---|
| 136 | #define SYSCONPBORCTL_BORIOR BSP_BIT32(1) |
|---|
| 137 | uint32_t pborctl; |
|---|
| 138 | |
|---|
| 139 | #define SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5) |
|---|
| 140 | #define SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5) |
|---|
| 141 | uint32_t ldopctl; |
|---|
| 142 | |
|---|
| 143 | uint32_t reserved_2[2]; |
|---|
| 144 | |
|---|
| 145 | uint32_t srcr0; |
|---|
| 146 | uint32_t srcr1; |
|---|
| 147 | uint32_t srcr2; |
|---|
| 148 | |
|---|
| 149 | uint32_t reserved_3; |
|---|
| 150 | |
|---|
| 151 | #define SYSCONRIS_MOSCPUPRIS BSP_BIT32(8) |
|---|
| 152 | #define SYSCONRIS_USBPLLRIS BSP_BIT32(7) |
|---|
| 153 | #define SYSCONRIS_PLLLRIS BSP_BIT32(6) |
|---|
| 154 | #define SYSCONRIS_BORRIS BSP_BIT32(1) |
|---|
| 155 | uint32_t ris; |
|---|
| 156 | |
|---|
| 157 | #define SYSCONIMC_MOSCPUPIM BSP_BIT32(8) |
|---|
| 158 | #define SYSCONIMC_USBPLLLIM BSP_BIT32(7) |
|---|
| 159 | #define SYSCONIMC_PLLLIM BSP_BIT32(6) |
|---|
| 160 | #define SYSCONIMC_BORIM BSP_BIT32(1) |
|---|
| 161 | uint32_t imc; |
|---|
| 162 | |
|---|
| 163 | #define SYSCONMISC_MOSCPUPMIS BSP_BIT32(8) |
|---|
| 164 | #define SYSCONMISC_USBPLLLMIS BSP_BIT32(7) |
|---|
| 165 | #define SYSCONMISC_PLLLMIS BSP_BIT32(6) |
|---|
| 166 | #define SYSCONMISC_BORMIS BSP_BIT32(1) |
|---|
| 167 | uint32_t misc; |
|---|
| 168 | |
|---|
| 169 | #define SYSCONRESC_MOSCFAIL BSP_BIT32(16) |
|---|
| 170 | #define SYSCONRESC_SW BSP_BIT32(4) |
|---|
| 171 | #define SYSCONRESC_WDT BSP_BIT32(3) |
|---|
| 172 | #define SYSCONRESC_BOR BSP_BIT32(2) |
|---|
| 173 | #define SYSCONRESC_POR BSP_BIT32(1) |
|---|
| 174 | #define SYSCONRESC_EXT BSP_BIT32(0) |
|---|
| 175 | uint32_t resc; |
|---|
| 176 | |
|---|
| 177 | #define SYSCONRCC_AGC BSP_BIT32(27) |
|---|
| 178 | #define SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26) |
|---|
| 179 | #define SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26) |
|---|
| 180 | #define SYSCONRCC_USESYSDIV BSP_BIT32(22) |
|---|
| 181 | #define SYSCONRCC_USEPWMDIV BSP_BIT32(20) |
|---|
| 182 | #define SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19) |
|---|
| 183 | #define SYSCONRCC_PWMDIV_DIV2_VAL 0 |
|---|
| 184 | #define SYSCONRCC_PWMDIV_DIV4_VAL 1 |
|---|
| 185 | #define SYSCONRCC_PWMDIV_DIV8_VAL 2 |
|---|
| 186 | #define SYSCONRCC_PWMDIV_DIV16_VAL 3 |
|---|
| 187 | #define SYSCONRCC_PWMDIV_DIV32_VAL 4 |
|---|
| 188 | #define SYSCONRCC_PWMDIV_DIV64_VAL 5 |
|---|
| 189 | #define SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19) |
|---|
| 190 | #define SYSCONRCC_PWRDN BSP_BIT32(13) |
|---|
| 191 | #define SYSCONRCC_BYPASS BSP_BIT32(11) |
|---|
| 192 | #define SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10) |
|---|
| 193 | #define SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10) |
|---|
| 194 | #define SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5) |
|---|
| 195 | #define SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0) |
|---|
| 196 | #define SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1) |
|---|
| 197 | #define SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2) |
|---|
| 198 | #define SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3) |
|---|
| 199 | #define SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5) |
|---|
| 200 | #define SYSCONRCC_IOSCDIS BSP_BIT32(1) |
|---|
| 201 | #define SYSCONRCC_MOSCDIS BSP_BIT32(0) |
|---|
| 202 | uint32_t rcc; |
|---|
| 203 | |
|---|
| 204 | #define SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13) |
|---|
| 205 | #define SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13) |
|---|
| 206 | #define SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4) |
|---|
| 207 | #define SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4) |
|---|
| 208 | uint32_t pllcfg; |
|---|
| 209 | |
|---|
| 210 | uint32_t reserved_4; |
|---|
| 211 | |
|---|
| 212 | #define SYSCONGPIOHBCTL_PORTH BSP_BIT32(7) |
|---|
| 213 | #define SYSCONGPIOHBCTL_PORTG BSP_BIT32(6) |
|---|
| 214 | #define SYSCONGPIOHBCTL_PORTF BSP_BIT32(5) |
|---|
| 215 | #define SYSCONGPIOHBCTL_PORTE BSP_BIT32(4) |
|---|
| 216 | #define SYSCONGPIOHBCTL_PORTD BSP_BIT32(3) |
|---|
| 217 | #define SYSCONGPIOHBCTL_PORTC BSP_BIT32(2) |
|---|
| 218 | #define SYSCONGPIOHBCTL_PORTB BSP_BIT32(1) |
|---|
| 219 | #define SYSCONGPIOHBCTL_PORTA BSP_BIT32(0) |
|---|
| 220 | uint32_t gpiohbctl; |
|---|
| 221 | |
|---|
| 222 | #define SYSCONRCC2_USERCC2 BSP_BIT32(31) |
|---|
| 223 | #define SYSCONRCC2_DIV400 BSP_BIT32(30) |
|---|
| 224 | #define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28) |
|---|
| 225 | #define SYSCONRCC2_SYSDIV2_MSK BSP_MSK32(23, 28) |
|---|
| 226 | #define SYSCONRCC2_SYSDIV2EXT(val) BSP_FLD32(val, 22, 28) |
|---|
| 227 | #define SYSCONRCC2_SYSDIV2EXT_MSK BSP_MSK32(22, 28) |
|---|
| 228 | #define SYSCONRCC2_USBPWRDN BSP_BIT32(14) |
|---|
| 229 | #define SYSCONRCC2_PWRDN2 BSP_BIT32(13) |
|---|
| 230 | #define SYSCONRCC2_BYPASS2 BSP_BIT32(11) |
|---|
| 231 | #define SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6) |
|---|
| 232 | #define SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6) |
|---|
| 233 | uint32_t rcc2; |
|---|
| 234 | |
|---|
| 235 | uint32_t reserved_5[2]; |
|---|
| 236 | |
|---|
| 237 | #define SYSCONMOSCCTL_CVAL BSP_BIT32(0) |
|---|
| 238 | uint32_t moscctl; |
|---|
| 239 | |
|---|
| 240 | uint32_t reserved_6[32]; |
|---|
| 241 | |
|---|
| 242 | #define SYSCONRCGC0_PWM BSP_BIT32(20) |
|---|
| 243 | #define SYSCONRCGC0_ADC BSP_BIT32(16) |
|---|
| 244 | #define SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9) |
|---|
| 245 | #define SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9) |
|---|
| 246 | #define SYSCONRCGC0_HIB BSP_BIT32(6) |
|---|
| 247 | #define SYSCONRCGC0_WDT BSP_BIT32(3) |
|---|
| 248 | uint32_t rcgc0; |
|---|
| 249 | |
|---|
| 250 | #define SYSCONRCGC1_COMP1 BSP_BIT32(25) |
|---|
| 251 | #define SYSCONRCGC1_COMP0 BSP_BIT32(24) |
|---|
| 252 | #define SYSCONRCGC1_TIMER3 BSP_BIT32(19) |
|---|
| 253 | #define SYSCONRCGC1_TIMER2 BSP_BIT32(18) |
|---|
| 254 | #define SYSCONRCGC1_TIMER1 BSP_BIT32(17) |
|---|
| 255 | #define SYSCONRCGC1_TIMER0 BSP_BIT32(16) |
|---|
| 256 | #define SYSCONRCGC1_I2C1 BSP_BIT32(14) |
|---|
| 257 | #define SYSCONRCGC1_I2C0 BSP_BIT32(12) |
|---|
| 258 | #define SYSCONRCGC1_QEI0 BSP_BIT32(8) |
|---|
| 259 | #if LM3S69XX_NUM_SSI_BLOCKS > 1 |
|---|
| 260 | #define SYSCONRCGC1_SSI1 BSP_BIT32(5) |
|---|
| 261 | #endif |
|---|
| 262 | #define SYSCONRCGC1_SSI0 BSP_BIT32(4) |
|---|
| 263 | #define SYSCONRCGC1_UART2 BSP_BIT32(2) |
|---|
| 264 | #define SYSCONRCGC1_UART1 BSP_BIT32(1) |
|---|
| 265 | #define SYSCONRCGC1_UART0 BSP_BIT32(0) |
|---|
| 266 | uint32_t rcgc1; |
|---|
| 267 | |
|---|
| 268 | #define SYSCONRCGC2_USB0 BSP_BIT32(16) |
|---|
| 269 | #define SYSCONRCGC2_UDMA BSP_BIT32(13) |
|---|
| 270 | #if LM3S69XX_NUM_GPIO_BLOCKS > 7 |
|---|
| 271 | #define SYSCONRCGC2_GPIOH BSP_BIT32(7) |
|---|
| 272 | #endif |
|---|
| 273 | #define SYSCONRCGC2_GPIOG BSP_BIT32(6) |
|---|
| 274 | #define SYSCONRCGC2_GPIOF BSP_BIT32(5) |
|---|
| 275 | #define SYSCONRCGC2_GPIOE BSP_BIT32(4) |
|---|
| 276 | #define SYSCONRCGC2_GPIOD BSP_BIT32(3) |
|---|
| 277 | #define SYSCONRCGC2_GPIOC BSP_BIT32(2) |
|---|
| 278 | #define SYSCONRCGC2_GPIOB BSP_BIT32(1) |
|---|
| 279 | #define SYSCONRCGC2_GPIOA BSP_BIT32(0) |
|---|
| 280 | uint32_t rcgc2; |
|---|
| 281 | |
|---|
| 282 | uint32_t reserved_7; |
|---|
| 283 | |
|---|
| 284 | uint32_t scgc0; |
|---|
| 285 | uint32_t scgc1; |
|---|
| 286 | uint32_t scgc2; |
|---|
| 287 | |
|---|
| 288 | uint32_t reserved_8; |
|---|
| 289 | |
|---|
| 290 | uint32_t dcgc0; |
|---|
| 291 | uint32_t dcgc1; |
|---|
| 292 | uint32_t dcgc2; |
|---|
| 293 | |
|---|
| 294 | uint32_t reserved_9[6]; |
|---|
| 295 | |
|---|
| 296 | #define SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28) |
|---|
| 297 | #define SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28) |
|---|
| 298 | #define SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6) |
|---|
| 299 | #define SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6) |
|---|
| 300 | uint32_t dslpclkcfg; |
|---|
| 301 | } lm3s69xx_syscon; |
|---|
| 302 | |
|---|
| 303 | typedef struct { |
|---|
| 304 | #define UARTDR_OE BSP_BIT32(11) |
|---|
| 305 | #define UARTDR_BE BSP_BIT32(10) |
|---|
| 306 | #define UARTDR_PE BSP_BIT32(9) |
|---|
| 307 | #define UARTDR_FE BSP_BIT32(8) |
|---|
| 308 | #define UARTDR_ERROR_MSK BSP_MSK32(8, 11) |
|---|
| 309 | #define UARTDR_DATA(val) BSP_FLD32(val, 0, 7) |
|---|
| 310 | #define UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) |
|---|
| 311 | uint32_t dr; |
|---|
| 312 | |
|---|
| 313 | uint32_t rsr_ecr; |
|---|
| 314 | uint32_t reserved_0[4]; |
|---|
| 315 | |
|---|
| 316 | #define UARTFR_TXFE BSP_BIT32(7) |
|---|
| 317 | #define UARTFR_RXFF BSP_BIT32(6) |
|---|
| 318 | #define UARTFR_TXFF BSP_BIT32(5) |
|---|
| 319 | #define UARTFR_RXFE BSP_BIT32(4) |
|---|
| 320 | #define UARTFR_BUSY BSP_BIT32(3) |
|---|
| 321 | uint32_t fr; |
|---|
| 322 | |
|---|
| 323 | uint32_t reserved_1; |
|---|
| 324 | |
|---|
| 325 | uint32_t ilpr; |
|---|
| 326 | uint32_t ibrd; |
|---|
| 327 | uint32_t fbrd; |
|---|
| 328 | |
|---|
| 329 | #define UARTLCRH_SPS BSP_BIT32(7) |
|---|
| 330 | #define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6) |
|---|
| 331 | #define UARTLCRH_FEN BSP_BIT32(4) |
|---|
| 332 | #define UARTLCRH_STP2 BSP_BIT32(3) |
|---|
| 333 | #define UARTLCRH_EPS BSP_BIT32(2) |
|---|
| 334 | #define UARTLCRH_PEN BSP_BIT32(1) |
|---|
| 335 | #define UARTLCRH_BRK BSP_BIT32(0) |
|---|
| 336 | uint32_t lcrh; |
|---|
| 337 | |
|---|
| 338 | #define UARTCTL_RXE BSP_BIT32(9) |
|---|
| 339 | #define UARTCTL_TXE BSP_BIT32(8) |
|---|
| 340 | #define UARTCTL_LBE BSP_BIT32(7) |
|---|
| 341 | #define UARTCTL_SIRLP BSP_BIT32(2) |
|---|
| 342 | #define UARTCTL_SIREN BSP_BIT32(1) |
|---|
| 343 | #define UARTCTL_UARTEN BSP_BIT32(0) |
|---|
| 344 | uint32_t ctl; |
|---|
| 345 | |
|---|
| 346 | #define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) |
|---|
| 347 | #define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) |
|---|
| 348 | uint32_t ifls; |
|---|
| 349 | |
|---|
| 350 | #define UARTI_OE BSP_BIT32(10) |
|---|
| 351 | #define UARTI_BE BSP_BIT32(9) |
|---|
| 352 | #define UARTI_PE BSP_BIT32(8) |
|---|
| 353 | #define UARTI_FE BSP_BIT32(7) |
|---|
| 354 | #define UARTI_RT BSP_BIT32(6) |
|---|
| 355 | #define UARTI_TX BSP_BIT32(5) |
|---|
| 356 | #define UARTI_RX BSP_BIT32(4) |
|---|
| 357 | uint32_t im; |
|---|
| 358 | uint32_t ris; |
|---|
| 359 | uint32_t mis; |
|---|
| 360 | uint32_t icr; |
|---|
| 361 | #if LM3S69XX_HAS_UDMA |
|---|
| 362 | uint32_t dmactl; |
|---|
| 363 | #endif |
|---|
| 364 | } lm3s69xx_uart; |
|---|
| 365 | |
|---|
| 366 | typedef struct { |
|---|
| 367 | #define SSICR0_SCR(val) BSP_FLD32(val, 8, 15) |
|---|
| 368 | #define SSICR0_SPH BSP_BIT32(7) |
|---|
| 369 | #define SSICR0_SPO BSP_BIT32(6) |
|---|
| 370 | #define SSICR0_FRF(val) BSP_FLD32(val, 4, 5) |
|---|
| 371 | #define SSICR0_DSS(val) BSP_FLD32(val, 0, 3) |
|---|
| 372 | uint32_t cr0; |
|---|
| 373 | |
|---|
| 374 | #define SSICR1_SOD BSP_BIT32(3) |
|---|
| 375 | #define SSICR1_MS BSP_BIT32(2) |
|---|
| 376 | #define SSICR1_SSE BSP_BIT32(1) |
|---|
| 377 | #define SSICR1_LBM BSP_BIT32(0) |
|---|
| 378 | uint32_t cr1; |
|---|
| 379 | uint32_t dr; |
|---|
| 380 | |
|---|
| 381 | #define SSISR_BSY BSP_BIT32(4) |
|---|
| 382 | #define SSISR_RFF BSP_BIT32(3) |
|---|
| 383 | #define SSISR_RNE BSP_BIT32(2) |
|---|
| 384 | #define SSISR_TNF BSP_BIT32(1) |
|---|
| 385 | #define SSISR_TFE BSP_BIT32(0) |
|---|
| 386 | uint32_t sr; |
|---|
| 387 | |
|---|
| 388 | #define SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7) |
|---|
| 389 | uint32_t cpsr; |
|---|
| 390 | |
|---|
| 391 | #define SSII_TX BSP_BIT32(3) |
|---|
| 392 | #define SSII_RX BSP_BIT32(2) |
|---|
| 393 | #define SSII_RT BSP_BIT32(1) |
|---|
| 394 | #define SSII_ROR BSP_BIT32(0) |
|---|
| 395 | uint32_t im; |
|---|
| 396 | uint32_t ris; |
|---|
| 397 | uint32_t mis; |
|---|
| 398 | uint32_t icr; |
|---|
| 399 | |
|---|
| 400 | #if LM3S69XX_HAS_UDMA |
|---|
| 401 | #define SSIDMACTL_TXDMAE BSP_BIT32(1) |
|---|
| 402 | #define SSIDMACTL_RXDMAE BSP_BIT32(0) |
|---|
| 403 | uint32_t dmactl; |
|---|
| 404 | #endif /* LM3S69XX_HAS_UDMA */ |
|---|
| 405 | } lm3s69xx_ssi; |
|---|
| 406 | |
|---|
| 407 | #endif /* LIBBSP_ARM_LM3S69XX_LM3S69XX_H */ |
|---|
![[RTEMS Logo]](/images/logo.png){kind=logo}
