[d970738] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lm3s69xx_reg |
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| 5 | * |
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| 6 | * @brief Register definitions. |
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| 7 | */ |
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| 8 | |
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[e263c16] | 9 | /* |
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[f22bba3] | 10 | * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> |
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| 11 | * |
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[e263c16] | 12 | * Copyright (c) 2011 Sebastian Huber. All rights reserved. |
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| 13 | * |
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| 14 | * embedded brains GmbH |
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| 15 | * Obere Lagerstr. 30 |
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| 16 | * 82178 Puchheim |
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| 17 | * Germany |
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| 18 | * <rtems@embedded-brains.de> |
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| 19 | * |
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| 20 | * The license and distribution terms for this file may be |
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| 21 | * found in the file LICENSE in this distribution or at |
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[c499856] | 22 | * http://www.rtems.org/license/LICENSE. |
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[e263c16] | 23 | */ |
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| 24 | |
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| 25 | #ifndef LIBBSP_ARM_LM3S69XX_LM3S69XX_H |
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| 26 | #define LIBBSP_ARM_LM3S69XX_LM3S69XX_H |
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[f22bba3] | 27 | #include <bspopts.h> |
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| 28 | #include <bsp/utility.h> |
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[e263c16] | 29 | |
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[d970738] | 30 | /** |
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| 31 | * @defgroup lm3s69xx_reg Register Definitions |
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| 32 | * |
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| 33 | * @ingroup arm_lm3s69xx |
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| 34 | * |
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| 35 | * @brief Register Definitions |
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| 36 | */ |
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| 37 | |
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[f22bba3] | 38 | #define LM3S69XX_SYSCON_BASE 0x400fe000 |
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[e263c16] | 39 | |
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| 40 | #define LM3S69XX_UART_0_BASE 0x4000c000 |
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| 41 | #define LM3S69XX_UART_1_BASE 0x4000d000 |
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| 42 | #define LM3S69XX_UART_2_BASE 0x4000e000 |
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| 43 | |
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[f22bba3] | 44 | #ifdef LM3S69XX_USE_AHB_FOR_GPIO |
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| 45 | #define LM3S69XX_GPIO_A_BASE 0x40058000 |
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| 46 | #define LM3S69XX_GPIO_B_BASE 0x40059000 |
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| 47 | #define LM3S69XX_GPIO_C_BASE 0x4005a000 |
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| 48 | #define LM3S69XX_GPIO_D_BASE 0x4005b000 |
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| 49 | #define LM3S69XX_GPIO_E_BASE 0x4005c000 |
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| 50 | #define LM3S69XX_GPIO_F_BASE 0x4005d000 |
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[0c47440] | 51 | #if LM3S69XX_NUM_GPIO_BLOCKS > 6 |
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[f22bba3] | 52 | #define LM3S69XX_GPIO_G_BASE 0x4005e000 |
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| 53 | #if LM3S69XX_NUM_GPIO_BLOCKS > 7 |
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| 54 | #define LM3S69XX_GPIO_H_BASE 0x4005f000 |
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| 55 | #endif |
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[0c47440] | 56 | #endif |
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[f22bba3] | 57 | |
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| 58 | #define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(LM3S69XX_GPIO_A_BASE + (port) * 0x1000)) |
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| 59 | #else /* LM3S69XX_USE_AHB_FOR_GPIO */ |
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| 60 | #define LM3S69XX_GPIO_A_BASE 0x40004000 |
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| 61 | #define LM3S69XX_GPIO_B_BASE 0x40005000 |
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| 62 | #define LM3S69XX_GPIO_C_BASE 0x40006000 |
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| 63 | #define LM3S69XX_GPIO_D_BASE 0x40007000 |
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| 64 | #define LM3S69XX_GPIO_E_BASE 0x40024000 |
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| 65 | #define LM3S69XX_GPIO_F_BASE 0x40025000 |
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[0c47440] | 66 | #if LM3S69XX_NUM_GPIO_BLOCKS > 6 |
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[f22bba3] | 67 | #define LM3S69XX_GPIO_G_BASE 0x40026000 |
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| 68 | #if LM3S69XX_NUM_GPIO_BLOCKS > 7 |
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| 69 | #define LM3S69XX_GPIO_H_BASE 0x40027000 |
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| 70 | #endif |
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[0c47440] | 71 | #endif |
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[f22bba3] | 72 | |
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| 73 | #define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(((port) < 4) ? \ |
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| 74 | (LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \ |
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| 75 | (LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000))) |
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| 76 | #endif /* LM3S69XX_USE_AHB_FOR_GPIO */ |
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| 77 | |
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| 78 | #define LM3S69XX_SSI_0_BASE 0x40008000 |
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| 79 | #if LM3S69XX_NUM_SSI_BLOCKS > 1 |
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| 80 | #define LM3S69XX_SSI_1_BASE 0x40009000 |
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[0c47440] | 81 | #if LM3S69XX_NUM_SSI_BLOCKS > 2 |
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| 82 | #define LM3S69XX_SSI_2_BASE 0x4000A000 |
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| 83 | #if LM3S69XX_NUM_SSI_BLOCKS > 3 |
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| 84 | #define LM3S69XX_SSI_3_BASE 0x4000B000 |
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| 85 | #endif |
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| 86 | #endif |
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[f22bba3] | 87 | #endif |
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| 88 | |
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| 89 | #define LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE) |
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| 90 | |
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| 91 | #define LM3S69XX_PLL_FREQUENCY 400000000U |
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| 92 | |
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| 93 | typedef struct { |
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| 94 | uint32_t data[256]; /* Masked data registers are included here. */ |
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| 95 | uint32_t dir; |
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| 96 | uint32_t is; |
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| 97 | uint32_t ibe; |
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| 98 | uint32_t iev; |
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| 99 | uint32_t im; |
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| 100 | uint32_t ris; |
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| 101 | uint32_t mis; |
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| 102 | uint32_t icr; |
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| 103 | uint32_t afsel; |
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| 104 | |
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| 105 | uint32_t reserved_0[55]; |
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| 106 | |
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| 107 | uint32_t dr2r; |
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| 108 | uint32_t dr4r; |
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| 109 | uint32_t dr8r; |
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| 110 | uint32_t odr; |
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| 111 | uint32_t pur; |
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| 112 | uint32_t pdr; |
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| 113 | uint32_t slr; |
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| 114 | uint32_t den; |
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| 115 | uint32_t lock; |
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| 116 | uint32_t cr; |
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| 117 | uint32_t amsel; |
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| 118 | } lm3s69xx_gpio; |
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| 119 | |
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| 120 | typedef struct { |
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| 121 | uint32_t did0; |
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| 122 | uint32_t did1; |
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| 123 | |
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| 124 | uint32_t dc0; |
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| 125 | uint32_t reserved_0; |
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| 126 | uint32_t dc1; |
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| 127 | uint32_t dc2; |
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| 128 | uint32_t dc3; |
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| 129 | uint32_t dc4; |
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| 130 | uint32_t dc5; |
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| 131 | uint32_t dc6; |
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| 132 | uint32_t dc7; |
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| 133 | |
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| 134 | uint32_t reserved_1; |
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| 135 | |
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| 136 | #define SYSCONPBORCTL_BORIOR BSP_BIT32(1) |
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| 137 | uint32_t pborctl; |
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| 138 | |
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| 139 | #define SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5) |
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| 140 | #define SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5) |
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| 141 | uint32_t ldopctl; |
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| 142 | |
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| 143 | uint32_t reserved_2[2]; |
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| 144 | |
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| 145 | uint32_t srcr0; |
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| 146 | uint32_t srcr1; |
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| 147 | uint32_t srcr2; |
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| 148 | |
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| 149 | uint32_t reserved_3; |
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| 150 | |
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| 151 | #define SYSCONRIS_MOSCPUPRIS BSP_BIT32(8) |
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| 152 | #define SYSCONRIS_USBPLLRIS BSP_BIT32(7) |
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| 153 | #define SYSCONRIS_PLLLRIS BSP_BIT32(6) |
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| 154 | #define SYSCONRIS_BORRIS BSP_BIT32(1) |
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| 155 | uint32_t ris; |
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| 156 | |
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| 157 | #define SYSCONIMC_MOSCPUPIM BSP_BIT32(8) |
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| 158 | #define SYSCONIMC_USBPLLLIM BSP_BIT32(7) |
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| 159 | #define SYSCONIMC_PLLLIM BSP_BIT32(6) |
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| 160 | #define SYSCONIMC_BORIM BSP_BIT32(1) |
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| 161 | uint32_t imc; |
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| 162 | |
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| 163 | #define SYSCONMISC_MOSCPUPMIS BSP_BIT32(8) |
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| 164 | #define SYSCONMISC_USBPLLLMIS BSP_BIT32(7) |
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| 165 | #define SYSCONMISC_PLLLMIS BSP_BIT32(6) |
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| 166 | #define SYSCONMISC_BORMIS BSP_BIT32(1) |
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| 167 | uint32_t misc; |
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| 168 | |
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| 169 | #define SYSCONRESC_MOSCFAIL BSP_BIT32(16) |
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| 170 | #define SYSCONRESC_SW BSP_BIT32(4) |
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| 171 | #define SYSCONRESC_WDT BSP_BIT32(3) |
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| 172 | #define SYSCONRESC_BOR BSP_BIT32(2) |
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| 173 | #define SYSCONRESC_POR BSP_BIT32(1) |
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| 174 | #define SYSCONRESC_EXT BSP_BIT32(0) |
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| 175 | uint32_t resc; |
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| 176 | |
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| 177 | #define SYSCONRCC_AGC BSP_BIT32(27) |
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| 178 | #define SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26) |
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| 179 | #define SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26) |
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| 180 | #define SYSCONRCC_USESYSDIV BSP_BIT32(22) |
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| 181 | #define SYSCONRCC_USEPWMDIV BSP_BIT32(20) |
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| 182 | #define SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19) |
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| 183 | #define SYSCONRCC_PWMDIV_DIV2_VAL 0 |
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| 184 | #define SYSCONRCC_PWMDIV_DIV4_VAL 1 |
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| 185 | #define SYSCONRCC_PWMDIV_DIV8_VAL 2 |
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| 186 | #define SYSCONRCC_PWMDIV_DIV16_VAL 3 |
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| 187 | #define SYSCONRCC_PWMDIV_DIV32_VAL 4 |
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| 188 | #define SYSCONRCC_PWMDIV_DIV64_VAL 5 |
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| 189 | #define SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19) |
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| 190 | #define SYSCONRCC_PWRDN BSP_BIT32(13) |
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| 191 | #define SYSCONRCC_BYPASS BSP_BIT32(11) |
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| 192 | #define SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10) |
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| 193 | #define SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10) |
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| 194 | #define SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5) |
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| 195 | #define SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0) |
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| 196 | #define SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1) |
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| 197 | #define SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2) |
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| 198 | #define SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3) |
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| 199 | #define SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5) |
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| 200 | #define SYSCONRCC_IOSCDIS BSP_BIT32(1) |
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| 201 | #define SYSCONRCC_MOSCDIS BSP_BIT32(0) |
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| 202 | uint32_t rcc; |
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| 203 | |
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| 204 | #define SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13) |
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| 205 | #define SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13) |
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| 206 | #define SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4) |
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| 207 | #define SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4) |
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| 208 | uint32_t pllcfg; |
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| 209 | |
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| 210 | uint32_t reserved_4; |
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| 211 | |
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| 212 | #define SYSCONGPIOHBCTL_PORTH BSP_BIT32(7) |
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| 213 | #define SYSCONGPIOHBCTL_PORTG BSP_BIT32(6) |
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| 214 | #define SYSCONGPIOHBCTL_PORTF BSP_BIT32(5) |
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| 215 | #define SYSCONGPIOHBCTL_PORTE BSP_BIT32(4) |
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| 216 | #define SYSCONGPIOHBCTL_PORTD BSP_BIT32(3) |
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| 217 | #define SYSCONGPIOHBCTL_PORTC BSP_BIT32(2) |
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| 218 | #define SYSCONGPIOHBCTL_PORTB BSP_BIT32(1) |
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| 219 | #define SYSCONGPIOHBCTL_PORTA BSP_BIT32(0) |
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| 220 | uint32_t gpiohbctl; |
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| 221 | |
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| 222 | #define SYSCONRCC2_USERCC2 BSP_BIT32(31) |
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[0c47440] | 223 | #define SYSCONRCC2_DIV400 BSP_BIT32(30) |
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[f22bba3] | 224 | #define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28) |
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[0c47440] | 225 | #define SYSCONRCC2_SYSDIV2_MSK BSP_MSK32(23, 28) |
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| 226 | #define SYSCONRCC2_SYSDIV2EXT(val) BSP_FLD32(val, 22, 28) |
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| 227 | #define SYSCONRCC2_SYSDIV2EXT_MSK BSP_MSK32(22, 28) |
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[f22bba3] | 228 | #define SYSCONRCC2_USBPWRDN BSP_BIT32(14) |
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| 229 | #define SYSCONRCC2_PWRDN2 BSP_BIT32(13) |
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| 230 | #define SYSCONRCC2_BYPASS2 BSP_BIT32(11) |
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| 231 | #define SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6) |
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| 232 | #define SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6) |
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| 233 | uint32_t rcc2; |
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| 234 | |
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| 235 | uint32_t reserved_5[2]; |
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| 236 | |
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| 237 | #define SYSCONMOSCCTL_CVAL BSP_BIT32(0) |
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| 238 | uint32_t moscctl; |
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| 239 | |
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| 240 | uint32_t reserved_6[32]; |
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| 241 | |
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| 242 | #define SYSCONRCGC0_PWM BSP_BIT32(20) |
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| 243 | #define SYSCONRCGC0_ADC BSP_BIT32(16) |
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| 244 | #define SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9) |
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| 245 | #define SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9) |
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| 246 | #define SYSCONRCGC0_HIB BSP_BIT32(6) |
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| 247 | #define SYSCONRCGC0_WDT BSP_BIT32(3) |
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| 248 | uint32_t rcgc0; |
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| 249 | |
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| 250 | #define SYSCONRCGC1_COMP1 BSP_BIT32(25) |
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| 251 | #define SYSCONRCGC1_COMP0 BSP_BIT32(24) |
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| 252 | #define SYSCONRCGC1_TIMER3 BSP_BIT32(19) |
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| 253 | #define SYSCONRCGC1_TIMER2 BSP_BIT32(18) |
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| 254 | #define SYSCONRCGC1_TIMER1 BSP_BIT32(17) |
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| 255 | #define SYSCONRCGC1_TIMER0 BSP_BIT32(16) |
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| 256 | #define SYSCONRCGC1_I2C1 BSP_BIT32(14) |
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| 257 | #define SYSCONRCGC1_I2C0 BSP_BIT32(12) |
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| 258 | #define SYSCONRCGC1_QEI0 BSP_BIT32(8) |
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| 259 | #if LM3S69XX_NUM_SSI_BLOCKS > 1 |
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| 260 | #define SYSCONRCGC1_SSI1 BSP_BIT32(5) |
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| 261 | #endif |
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| 262 | #define SYSCONRCGC1_SSI0 BSP_BIT32(4) |
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| 263 | #define SYSCONRCGC1_UART2 BSP_BIT32(2) |
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| 264 | #define SYSCONRCGC1_UART1 BSP_BIT32(1) |
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| 265 | #define SYSCONRCGC1_UART0 BSP_BIT32(0) |
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| 266 | uint32_t rcgc1; |
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| 267 | |
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| 268 | #define SYSCONRCGC2_USB0 BSP_BIT32(16) |
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| 269 | #define SYSCONRCGC2_UDMA BSP_BIT32(13) |
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| 270 | #if LM3S69XX_NUM_GPIO_BLOCKS > 7 |
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| 271 | #define SYSCONRCGC2_GPIOH BSP_BIT32(7) |
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| 272 | #endif |
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| 273 | #define SYSCONRCGC2_GPIOG BSP_BIT32(6) |
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| 274 | #define SYSCONRCGC2_GPIOF BSP_BIT32(5) |
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| 275 | #define SYSCONRCGC2_GPIOE BSP_BIT32(4) |
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| 276 | #define SYSCONRCGC2_GPIOD BSP_BIT32(3) |
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| 277 | #define SYSCONRCGC2_GPIOC BSP_BIT32(2) |
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| 278 | #define SYSCONRCGC2_GPIOB BSP_BIT32(1) |
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| 279 | #define SYSCONRCGC2_GPIOA BSP_BIT32(0) |
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| 280 | uint32_t rcgc2; |
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| 281 | |
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| 282 | uint32_t reserved_7; |
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| 283 | |
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| 284 | uint32_t scgc0; |
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| 285 | uint32_t scgc1; |
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| 286 | uint32_t scgc2; |
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| 287 | |
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| 288 | uint32_t reserved_8; |
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| 289 | |
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| 290 | uint32_t dcgc0; |
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| 291 | uint32_t dcgc1; |
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| 292 | uint32_t dcgc2; |
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| 293 | |
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| 294 | uint32_t reserved_9[6]; |
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| 295 | |
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| 296 | #define SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28) |
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| 297 | #define SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28) |
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| 298 | #define SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6) |
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| 299 | #define SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6) |
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| 300 | uint32_t dslpclkcfg; |
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| 301 | } lm3s69xx_syscon; |
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| 302 | |
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| 303 | typedef struct { |
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| 304 | #define UARTDR_OE BSP_BIT32(11) |
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| 305 | #define UARTDR_BE BSP_BIT32(10) |
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| 306 | #define UARTDR_PE BSP_BIT32(9) |
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| 307 | #define UARTDR_FE BSP_BIT32(8) |
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[847e2cac] | 308 | #define UARTDR_ERROR_MSK BSP_MSK32(8, 11) |
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[f22bba3] | 309 | #define UARTDR_DATA(val) BSP_FLD32(val, 0, 7) |
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[847e2cac] | 310 | #define UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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[f22bba3] | 311 | uint32_t dr; |
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| 312 | |
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| 313 | uint32_t rsr_ecr; |
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| 314 | uint32_t reserved_0[4]; |
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| 315 | |
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| 316 | #define UARTFR_TXFE BSP_BIT32(7) |
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| 317 | #define UARTFR_RXFF BSP_BIT32(6) |
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| 318 | #define UARTFR_TXFF BSP_BIT32(5) |
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| 319 | #define UARTFR_RXFE BSP_BIT32(4) |
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| 320 | #define UARTFR_BUSY BSP_BIT32(3) |
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| 321 | uint32_t fr; |
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| 322 | |
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| 323 | uint32_t reserved_1; |
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| 324 | |
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| 325 | uint32_t ilpr; |
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| 326 | uint32_t ibrd; |
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| 327 | uint32_t fbrd; |
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| 328 | |
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| 329 | #define UARTLCRH_SPS BSP_BIT32(7) |
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| 330 | #define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6) |
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| 331 | #define UARTLCRH_FEN BSP_BIT32(4) |
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| 332 | #define UARTLCRH_STP2 BSP_BIT32(3) |
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| 333 | #define UARTLCRH_EPS BSP_BIT32(2) |
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| 334 | #define UARTLCRH_PEN BSP_BIT32(1) |
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| 335 | #define UARTLCRH_BRK BSP_BIT32(0) |
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| 336 | uint32_t lcrh; |
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| 337 | |
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| 338 | #define UARTCTL_RXE BSP_BIT32(9) |
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| 339 | #define UARTCTL_TXE BSP_BIT32(8) |
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| 340 | #define UARTCTL_LBE BSP_BIT32(7) |
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| 341 | #define UARTCTL_SIRLP BSP_BIT32(2) |
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| 342 | #define UARTCTL_SIREN BSP_BIT32(1) |
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| 343 | #define UARTCTL_UARTEN BSP_BIT32(0) |
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| 344 | uint32_t ctl; |
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| 345 | |
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| 346 | #define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) |
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| 347 | #define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) |
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| 348 | uint32_t ifls; |
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| 349 | |
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| 350 | #define UARTI_OE BSP_BIT32(10) |
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| 351 | #define UARTI_BE BSP_BIT32(9) |
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| 352 | #define UARTI_PE BSP_BIT32(8) |
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| 353 | #define UARTI_FE BSP_BIT32(7) |
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| 354 | #define UARTI_RT BSP_BIT32(6) |
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| 355 | #define UARTI_TX BSP_BIT32(5) |
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| 356 | #define UARTI_RX BSP_BIT32(4) |
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| 357 | uint32_t im; |
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| 358 | uint32_t ris; |
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| 359 | uint32_t mis; |
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| 360 | uint32_t icr; |
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| 361 | #if LM3S69XX_HAS_UDMA |
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| 362 | uint32_t dmactl; |
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| 363 | #endif |
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| 364 | } lm3s69xx_uart; |
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| 365 | |
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| 366 | typedef struct { |
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| 367 | #define SSICR0_SCR(val) BSP_FLD32(val, 8, 15) |
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| 368 | #define SSICR0_SPH BSP_BIT32(7) |
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| 369 | #define SSICR0_SPO BSP_BIT32(6) |
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| 370 | #define SSICR0_FRF(val) BSP_FLD32(val, 4, 5) |
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| 371 | #define SSICR0_DSS(val) BSP_FLD32(val, 0, 3) |
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| 372 | uint32_t cr0; |
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| 373 | |
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| 374 | #define SSICR1_SOD BSP_BIT32(3) |
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| 375 | #define SSICR1_MS BSP_BIT32(2) |
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| 376 | #define SSICR1_SSE BSP_BIT32(1) |
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| 377 | #define SSICR1_LBM BSP_BIT32(0) |
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| 378 | uint32_t cr1; |
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| 379 | uint32_t dr; |
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| 380 | |
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| 381 | #define SSISR_BSY BSP_BIT32(4) |
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| 382 | #define SSISR_RFF BSP_BIT32(3) |
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| 383 | #define SSISR_RNE BSP_BIT32(2) |
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| 384 | #define SSISR_TNF BSP_BIT32(1) |
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| 385 | #define SSISR_TFE BSP_BIT32(0) |
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| 386 | uint32_t sr; |
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| 387 | |
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| 388 | #define SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7) |
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| 389 | uint32_t cpsr; |
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| 390 | |
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| 391 | #define SSII_TX BSP_BIT32(3) |
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| 392 | #define SSII_RX BSP_BIT32(2) |
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| 393 | #define SSII_RT BSP_BIT32(1) |
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| 394 | #define SSII_ROR BSP_BIT32(0) |
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| 395 | uint32_t im; |
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| 396 | uint32_t ris; |
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| 397 | uint32_t mis; |
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| 398 | uint32_t icr; |
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| 399 | |
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| 400 | #if LM3S69XX_HAS_UDMA |
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| 401 | #define SSIDMACTL_TXDMAE BSP_BIT32(1) |
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| 402 | #define SSIDMACTL_RXDMAE BSP_BIT32(0) |
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| 403 | uint32_t dmactl; |
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| 404 | #endif /* LM3S69XX_HAS_UDMA */ |
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| 405 | } lm3s69xx_ssi; |
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[e263c16] | 406 | |
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| 407 | #endif /* LIBBSP_ARM_LM3S69XX_LM3S69XX_H */ |
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