1 | /* |
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2 | * Copyright (c) 2013 Eugeniy Meshcheryakov <eugen@debian.org> |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | #include <bsp.h> |
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10 | #include <bspopts.h> |
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11 | #include <bsp/ssi.h> |
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12 | #include <bsp/syscon.h> |
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13 | #include <bsp/io.h> |
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14 | #include <bsp/lm3s69xx.h> |
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15 | |
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16 | typedef struct { |
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17 | rtems_libi2c_bus_t bus; |
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18 | volatile lm3s69xx_ssi *regs; |
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19 | int bus_number; |
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20 | uint16_t idle_char; |
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21 | uint8_t cs_pin; |
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22 | lm3s69xx_gpio_config io_configs[3]; |
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23 | } lm3s69xx_ssi_bus_entry; |
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24 | |
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25 | static rtems_status_code lm3s69xx_ssi_init(rtems_libi2c_bus_t *bus) |
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26 | { |
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27 | lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; |
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28 | volatile lm3s69xx_ssi* regs = e->regs; |
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29 | uint32_t clock_div = LM3S69XX_SYSTEM_CLOCK / 2 / LM3S69XX_SSI_CLOCK; |
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30 | |
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31 | lm3s69xx_gpio_set_config_array(e->io_configs, 3); |
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32 | |
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33 | lm3s69xx_syscon_enable_ssi_clock(e->bus_number, true); |
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34 | regs->cr1 = 0; |
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35 | regs->cpsr = SSI_CPSRDIV(2); |
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36 | regs->cr0 = SSICR0_SCR(clock_div - 1) | SSICR0_SPO | SSICR0_SPH | SSICR0_FRF(0) | SSICR0_DSS(7); |
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37 | regs->cr1 = SSICR1_SSE; |
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38 | |
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39 | return RTEMS_SUCCESSFUL; |
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40 | } |
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41 | |
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42 | static rtems_status_code lm3s69xx_ssi_send_start(rtems_libi2c_bus_t *bus) |
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43 | { |
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44 | return RTEMS_SUCCESSFUL; |
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45 | } |
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46 | |
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47 | static rtems_status_code lm3s69xx_ssi_send_stop(rtems_libi2c_bus_t *bus) |
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48 | { |
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49 | lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; |
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50 | volatile lm3s69xx_ssi* regs = e->regs; |
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51 | |
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52 | while ((regs->sr & SSISR_BSY) != 0) |
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53 | /* wait */; |
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54 | |
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55 | lm3s69xx_gpio_set_pin(e->cs_pin, true); |
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56 | |
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57 | return RTEMS_SUCCESSFUL; |
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58 | } |
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59 | |
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60 | static rtems_status_code lm3s69xx_ssi_send_addr(rtems_libi2c_bus_t *bus, |
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61 | uint32_t addr, int rw) |
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62 | { |
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63 | lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; |
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64 | e->cs_pin = addr; |
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65 | lm3s69xx_gpio_set_pin(e->cs_pin, false); |
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66 | |
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67 | return RTEMS_SUCCESSFUL; |
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68 | } |
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69 | |
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70 | static int lm3s69xx_ssi_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n) |
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71 | { |
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72 | lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; |
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73 | volatile lm3s69xx_ssi* regs = e->regs; |
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74 | int i; |
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75 | |
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76 | for (i = 0; i < n; i++) { |
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77 | while ((regs->sr & SSISR_TNF) == 0) |
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78 | /* wait */; |
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79 | |
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80 | regs->dr = e->idle_char; |
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81 | |
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82 | while ((regs->sr & SSISR_RNE) == 0) |
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83 | /* wait */; |
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84 | |
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85 | in[i] = regs->dr & 0xff; |
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86 | } |
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87 | |
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88 | return n; |
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89 | } |
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90 | |
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91 | static int lm3s69xx_ssi_write(rtems_libi2c_bus_t *bus, unsigned char *out, int n) |
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92 | { |
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93 | lm3s69xx_ssi_bus_entry *e = (lm3s69xx_ssi_bus_entry *)bus; |
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94 | volatile lm3s69xx_ssi* regs = e->regs; |
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95 | int i; |
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96 | |
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97 | for (i = 0; i < n; i++) { |
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98 | while ((regs->sr & SSISR_TNF) == 0) |
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99 | /* wait */; |
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100 | |
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101 | regs->dr = out[i]; |
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102 | |
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103 | while ((regs->sr & SSISR_RNE) == 0) |
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104 | /* wait */; |
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105 | |
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106 | uint32_t dummy = regs->dr; |
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107 | (void)dummy; |
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108 | } |
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109 | |
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110 | return n; |
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111 | } |
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112 | |
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113 | static int lm3s69xx_ssi_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg) |
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114 | { |
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115 | return -RTEMS_NOT_DEFINED; |
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116 | } |
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117 | |
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118 | static const rtems_libi2c_bus_ops_t lm3s69xx_ssi_ops = { |
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119 | .init = lm3s69xx_ssi_init, |
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120 | .send_start = lm3s69xx_ssi_send_start, |
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121 | .send_stop = lm3s69xx_ssi_send_stop, |
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122 | .send_addr = lm3s69xx_ssi_send_addr, |
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123 | .read_bytes = lm3s69xx_ssi_read, |
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124 | .write_bytes = lm3s69xx_ssi_write, |
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125 | .ioctl = lm3s69xx_ssi_ioctl |
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126 | }; |
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127 | |
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128 | static lm3s69xx_ssi_bus_entry ssi_0_bus = { |
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129 | .bus = { |
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130 | .ops = &lm3s69xx_ssi_ops, |
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131 | .size = sizeof(lm3s69xx_ssi_bus_entry) |
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132 | }, |
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133 | .regs = (volatile lm3s69xx_ssi *)LM3S69XX_SSI_0_BASE, |
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134 | .bus_number = 0, |
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135 | .idle_char = 0xffff, |
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136 | .io_configs = { |
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137 | #if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM3S6965) || defined(LM3S69XX_MCU_LM4F120) |
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138 | LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_A, 2), /* CLK */ |
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139 | LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_A, 5), /* TX */ |
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140 | LM3S69XX_PIN_SSI_RX(LM3S69XX_PORT_A, 4) /* RX */ |
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141 | #else |
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142 | #error No GPIO pin definitions for SSI 0 |
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143 | #endif |
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144 | } |
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145 | }; |
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146 | |
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147 | rtems_libi2c_bus_t * const lm3s69xx_ssi_0 = &ssi_0_bus.bus; |
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148 | |
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149 | #if LM3S69XX_NUM_SSI_BLOCKS > 1 |
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150 | static lm3s69xx_ssi_bus_entry ssi_1_bus = { |
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151 | .bus = { |
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152 | .ops = &lm3s69xx_ssi_ops, |
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153 | .size = sizeof(lm3s69xx_ssi_bus_entry) |
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154 | }, |
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155 | .regs = (volatile lm3s69xx_ssi *)LM3S69XX_SSI_1_BASE, |
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156 | .bus_number = 1, |
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157 | .idle_char = 0xffff, |
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158 | .io_configs = { |
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159 | #if defined(LM3S69XX_MCU_LM3S3749) || defined(LM3S69XX_MCU_LM4F120) |
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160 | LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_E, 0), /* CLK */ |
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161 | LM3S69XX_PIN_SSI_TX(LM3S69XX_PORT_E, 3), /* TX */ |
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162 | LM3S69XX_PIN_SSI_RX(LM3S69XX_PORT_E, 2) /* RX */ |
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163 | #else |
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164 | #error No GPIO pin definitions for SSI 1 |
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165 | #endif |
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166 | } |
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167 | }; |
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168 | |
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169 | rtems_libi2c_bus_t * const lm3s69xx_ssi_1 = &ssi_1_bus.bus; |
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170 | #endif /* LM3S69XX_NUM_SSI_BLOCKS > 1 */ |
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