1 | /* |
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2 | * Copyright (c) 2012 Claas Ziemke. All rights reserved. |
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3 | * |
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4 | * Claas Ziemke |
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5 | * Kernerstrasse 11 |
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6 | * 70182 Stuttgart |
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7 | * Germany |
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8 | * <claas.ziemke@gmx.net> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | * |
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14 | * Modified by Ben Gras <beng@shrike-systems.com> to add lots |
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15 | * of beagleboard/beaglebone definitions, delete lpc32xx specific |
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16 | * ones, and merge with some other header files. |
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17 | */ |
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18 | |
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19 | /* Interrupt controller memory map */ |
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20 | #define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ |
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21 | |
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22 | /* Interrupt controller memory map */ |
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23 | #define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ |
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24 | |
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25 | /* Interrupt controller registers */ |
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26 | #define OMAP3_INTCPS_REVISION 0x000 /* IP revision code */ |
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27 | #define OMAP3_INTCPS_SYSCONFIG 0x010 /* Controls params */ |
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28 | #define OMAP3_INTCPS_SYSSTATUS 0x014 /* Status */ |
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29 | #define OMAP3_INTCPS_SIR_IRQ 0x040 /* Active IRQ number */ |
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30 | #define OMAP3_INTCPS_SIR_FIQ 0x044 /* Active FIQ number */ |
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31 | #define OMAP3_INTCPS_CONTROL 0x048 /* New int agreement bits */ |
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32 | #define OMAP3_INTCPS_PROTECTION 0x04C /* Protection for other regs */ |
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33 | #define OMAP3_INTCPS_IDLE 0x050 /* Clock auto-idle/gating */ |
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34 | #define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */ |
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35 | #define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */ |
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36 | #define OMAP3_INTCPS_THRESHOLD 0x068 /* Priority threshold */ |
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37 | #define OMAP3_INTCPS_ITR0 0x080 /* Raw pre-masking interrupt status */ |
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38 | #define OMAP3_INTCPS_MIR0 0x084 /* Interrupt mask */ |
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39 | #define OMAP3_INTCPS_MIR1 0x0A4 /* Interrupt mask */ |
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40 | #define OMAP3_INTCPS_MIR2 0x0C4 /* Interrupt mask */ |
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41 | #define OMAP3_INTCPS_MIR3 0x0E4 /* Interrupt mask */ |
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42 | #define OMAP3_INTCPS_MIR_CLEAR0 0x088 /* Clear interrupt mask bits */ |
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43 | #define OMAP3_INTCPS_MIR_SET0 0x08C /* Set interrupt mask bits */ |
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44 | #define OMAP3_INTCPS_ISR_SET0 0x090 /* Set software int bits */ |
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45 | #define OMAP3_INTCPS_ISR_CLEAR0 0x094 /* Clear software int bits */ |
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46 | #define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */ |
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47 | #define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */ |
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48 | #define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */ |
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49 | #define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */ |
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50 | #define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */ |
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51 | #define OMAP3_INTCPS_ILR0 0x100 /* Priority for interrupts */ |
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52 | |
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53 | /* SYSCONFIG */ |
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54 | #define OMAP3_SYSCONFIG_AUTOIDLE 0x01 /* SYSCONFIG.AUTOIDLE bit */ |
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55 | |
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56 | #define OMAP3_INTR_ITR(base,n) \ |
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57 | (base + OMAP3_INTCPS_ITR0 + 0x20 * (n)) |
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58 | #define OMAP3_INTR_MIR(base,n) \ |
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59 | (base + OMAP3_INTCPS_MIR0 + 0x20 * (n)) |
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60 | #define OMAP3_INTR_MIR_CLEAR(base,n) \ |
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61 | (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n)) |
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62 | #define OMAP3_INTR_MIR_SET(base,n) \ |
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63 | (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n)) |
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64 | #define OMAP3_INTR_ISR_SET(base,n) \ |
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65 | (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n)) |
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66 | #define OMAP3_INTR_ISR_CLEAR(base,n) \ |
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67 | (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n)) |
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68 | #define OMAP3_INTR_PENDING_IRQ(base,n) \ |
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69 | (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n)) |
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70 | #define OMAP3_INTR_PENDING_FIQ(base,n) \ |
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71 | (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n)) |
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72 | #define OMAP3_INTR_ILR(base,m) \ |
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73 | (base + OMAP3_INTCPS_ILR0 + 0x4 * (m)) |
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74 | |
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75 | #define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */ |
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76 | #define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */ |
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77 | #define OMAP3_INTR_NEWIRQAGR 0x1 /* New IRQ Generation */ |
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78 | |
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79 | #define OMAP3_DM337X_NR_IRQ_VECTORS 96 |
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80 | |
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81 | /* Interrupt mappings */ |
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82 | #define OMAP3_MCBSP2_ST_IRQ 4 /* Sidestone McBSP2 overflow */ |
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83 | #define OMAP3_MCBSP3_ST_IRQ 5 /* Sidestone McBSP3 overflow */ |
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84 | #define OMAP3_SYS_NIRQ 7 /* External source (active low) */ |
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85 | #define OMAP3_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */ |
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86 | #define OMAP3_SMX_APP_IRQ 10 /* L3 interconnect error for application */ |
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87 | #define OMAP3_PRCM_IRQ 11 /* PRCM module */ |
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88 | #define OMAP3_SDMA0_IRQ 12 /* System DMA request 0 */ |
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89 | #define OMAP3_SDMA1_IRQ 13 /* System DMA request 1 */ |
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90 | #define OMAP3_SDMA2_IRQ 14 /* System DMA request 2 */ |
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91 | #define OMAP3_SDMA3_IRQ 15 /* System DMA request 3 */ |
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92 | #define OMAP3_MCBSP1_IRQ 16 /* McBSP module 1 */ |
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93 | #define OMAP3_MCBSP2_IRQ 17 /* McBSP module 2 */ |
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94 | #define OMAP3_GPMC_IRQ 20 /* General-purpose memory controller */ |
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95 | #define OMAP3_SGX_IRQ 21 /* 2D/3D graphics module */ |
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96 | #define OMAP3_MCBSP3_IRQ 22 /* McBSP module 3 */ |
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97 | #define OMAP3_MCBSP4_IRQ 23 /* McBSP module 4 */ |
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98 | #define OMAP3_CAM0_IRQ 24 /* Camera interface request 0 */ |
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99 | #define OMAP3_DSS_IRQ 25 /* Display subsystem module */ |
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100 | #define OMAP3_MAIL_U0_IRQ 26 /* Mailbox user 0 request */ |
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101 | #define OMAP3_MCBSP5_IRQ 27 /* McBSP module 5 */ |
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102 | #define OMAP3_IVA2_MMU_IRQ 28 /* IVA2 MMU */ |
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103 | #define OMAP3_GPIO1_IRQ 29 /* GPIO module 1 */ |
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104 | #define OMAP3_GPIO2_IRQ 30 /* GPIO module 2 */ |
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105 | #define OMAP3_GPIO3_IRQ 31 /* GPIO module 3 */ |
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106 | #define OMAP3_GPIO4_IRQ 32 /* GPIO module 4 */ |
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107 | #define OMAP3_GPIO5_IRQ 33 /* GPIO module 5 */ |
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108 | #define OMAP3_GPIO6_IRQ 34 /* GPIO module 6 */ |
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109 | #define OMAP3_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */ |
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110 | #define OMAP3_GPT1_IRQ 37 /* General-purpose timer module 1 */ |
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111 | #define OMAP3_GPT2_IRQ 38 /* General-purpose timer module 2 */ |
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112 | #define OMAP3_GPT3_IRQ 39 /* General-purpose timer module 3 */ |
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113 | #define OMAP3_GPT4_IRQ 40 /* General-purpose timer module 4 */ |
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114 | #define OMAP3_GPT5_IRQ 41 /* General-purpose timer module 5 */ |
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115 | #define OMAP3_GPT6_IRQ 42 /* General-purpose timer module 6 */ |
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116 | #define OMAP3_GPT7_IRQ 43 /* General-purpose timer module 7 */ |
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117 | #define OMAP3_GPT8_IRQ 44 /* General-purpose timer module 8 */ |
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118 | #define OMAP3_GPT9_IRQ 45 /* General-purpose timer module 9 */ |
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119 | #define OMAP3_GPT10_IRQ 46 /* General-purpose timer module 10 */ |
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120 | #define OMAP3_GPT11_IRQ 47 /* General-purpose timer module 11 */ |
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121 | #define OMAP3_SPI4_IRQ 48 /* McSPI module 4 */ |
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122 | #define OMAP3_MCBSP4_TX_IRQ 54 /* McBSP module 4 transmit */ |
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123 | #define OMAP3_MCBSP4_RX_IRQ 55 /* McBSP module 4 receive */ |
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124 | #define OMAP3_I2C1_IRQ 56 /* I2C module 1 */ |
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125 | #define OMAP3_I2C2_IRQ 57 /* I2C module 2 */ |
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126 | #define OMAP3_HDQ_IRQ 58 /* HDQ/1-Wire */ |
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127 | #define OMAP3_MCBSP1_TX_IRQ 59 /* McBSP module 1 transmit */ |
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128 | #define OMAP3_MCBSP1_RX_IRQ 60 /* McBSP module 1 receive */ |
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129 | #define OMAP3_I2C3_IRQ 61 /* I2C module 3 */ |
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130 | #define OMAP3_MCBSP2_TX_IRQ 62 /* McBSP module 2 transmit */ |
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131 | #define OMAP3_MCBSP2_RX_IRQ 63 /* McBSP module 2 receive */ |
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132 | #define OMAP3_SPI1_IRQ 65 /* McSPI module 1 */ |
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133 | #define OMAP3_SPI2_IRQ 66 /* McSPI module 2 */ |
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134 | #define OMAP3_UART1_IRQ 72 /* UART module 1 */ |
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135 | #define OMAP3_UART2_IRQ 73 /* UART module 2 */ |
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136 | #define OMAP3_UART3_IRQ 74 /* UART module 3 */ |
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137 | #define OMAP3_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite 1/2 */ |
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138 | #define OMAP3_OHCI_IRQ 76 /* OHCI HSUSB MP Host Interrupt */ |
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139 | #define OMAP3_EHCI_IRQ 77 /* EHCI HSUSB MP Host Interrupt */ |
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140 | #define OMAP3_TLL_IRQ 78 /* HSUSB MP TLL Interrupt */ |
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141 | #define OMAP3_MCBSP5_TX_IRQ 81 /* McBSP module 5 transmit */ |
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142 | #define OMAP3_MCBSP5_RX_IRQ 82 /* McBSP module 5 receive */ |
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143 | #define OMAP3_MMC1_IRQ 83 /* MMC/SD module 1 */ |
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144 | #define OMAP3_MMC2_IRQ 86 /* MMC/SD module 2 */ |
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145 | #define OMAP3_ICR_IRQ 87 /* MPU ICR */ |
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146 | #define OMAP3_D2DFRINT_IRQ 88 /* 3G coproc (in stacked modem config) */ |
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147 | #define OMAP3_MCBSP3_TX_IRQ 89 /* McBSP module 3 transmit */ |
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148 | #define OMAP3_MCBSP3_RX_IRQ 90 /* McBSP module 3 receive */ |
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149 | #define OMAP3_SPI3_IRQ 91 /* McSPI module 3 */ |
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150 | #define OMAP3_HSUSB_MC_IRQ 92 /* High-speed USB OTG */ |
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151 | #define OMAP3_HSUSB_DMA_IRQ 93 /* High-speed USB OTG DMA */ |
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152 | #define OMAP3_MMC3_IRQ 94 /* MMC/SD module 3 */ |
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153 | |
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154 | /* General-purpose timer register map */ |
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155 | #define OMAP3_GPTIMER1_BASE 0x48318000 |
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156 | /* GPTIMER1 physical address */ |
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157 | #define OMAP3_GPTIMER2_BASE 0x49032000 |
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158 | /* GPTIMER2 physical address */ |
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159 | #define OMAP3_GPTIMER3_BASE 0x49034000 |
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160 | /* GPTIMER3 physical address */ |
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161 | #define OMAP3_GPTIMER4_BASE 0x49036000 |
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162 | /* GPTIMER4 physical address */ |
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163 | #define OMAP3_GPTIMER5_BASE 0x49038000 |
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164 | /* GPTIMER5 physical address */ |
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165 | #define OMAP3_GPTIMER6_BASE 0x4903A000 |
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166 | /* GPTIMER6 physical address */ |
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167 | #define OMAP3_GPTIMER7_BASE 0x4903C000 |
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168 | /* GPTIMER7 physical address */ |
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169 | #define OMAP3_GPTIMER8_BASE 0x4903E000 |
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170 | /* GPTIMER8 physical address */ |
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171 | #define OMAP3_GPTIMER9_BASE 0x49040000 |
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172 | /* GPTIMER9 physical address */ |
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173 | #define OMAP3_GPTIMER10_BASE 0x48086000 |
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174 | /* GPTIMER10 physical address */ |
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175 | #define OMAP3_GPTIMER11_BASE 0x48088000 |
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176 | /* GPTIMER11 physical address */ |
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177 | |
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178 | |
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179 | /* General-purpose timer registers */ |
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180 | #define OMAP3_TIMER_TIDR 0x000 |
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181 | /* IP revision code */ |
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182 | #define OMAP3_TIMER_TIOCP_CFG 0x010 |
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183 | /* Controls params for GP timer L4 iface */ |
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184 | #define OMAP3_TIMER_TISTAT 0x014 |
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185 | /* Status (excl. interrupt status) */ |
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186 | #define OMAP3_TIMER_TISR 0x018 |
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187 | /* Pending interrupt status */ |
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188 | #define OMAP3_TIMER_TIER 0x01C |
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189 | /* Interrupt enable */ |
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190 | #define OMAP3_TIMER_TWER 0x020 |
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191 | /* Wakeup enable */ |
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192 | #define OMAP3_TIMER_TCLR 0x024 |
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193 | /* Controls optional features */ |
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194 | #define OMAP3_TIMER_TCRR 0x028 |
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195 | /* Internal counter value */ |
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196 | #define OMAP3_TIMER_TLDR 0x02C |
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197 | /* Timer load value */ |
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198 | #define OMAP3_TIMER_TTGR 0x030 |
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199 | /* Triggers counter reload */ |
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200 | #define OMAP3_TIMER_TWPS 0x034 |
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201 | /* Indicates if Write-Posted pending */ |
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202 | #define OMAP3_TIMER_TMAR 0x038 |
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203 | /* Value to be compared with counter */ |
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204 | #define OMAP3_TIMER_TCAR1 0x03C |
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205 | /* First captured value of counter reg */ |
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206 | #define OMAP3_TIMER_TSICR 0x040 |
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207 | /* Control posted mode and functional SW rst */ |
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208 | #define OMAP3_TIMER_TCAR2 0x044 |
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209 | /* Second captured value of counter register */ |
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210 | #define OMAP3_TIMER_TPIR 0x048 |
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211 | /* Positive increment (1 ms tick) */ |
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212 | #define OMAP3_TIMER_TNIR 0x04C |
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213 | /* Negative increment (1 ms tick) */ |
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214 | #define OMAP3_TIMER_TCVR 0x050 |
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215 | /* Defines TCRR is sub/over-period (1 ms tick) */ |
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216 | #define OMAP3_TIMER_TOCR 0x054 |
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217 | /* Masks tick interrupt */ |
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218 | #define OMAP3_TIMER_TOWR 0x058 |
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219 | /* Number of masked overflow interrupts */ |
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220 | |
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221 | /* Interrupt status register fields */ |
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222 | #define OMAP3_TISR_MAT_IT_FLAG (1 << 0) /* Pending match interrupt status */ |
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223 | #define OMAP3_TISR_OVF_IT_FLAG (1 << 1) /* Pending overflow interrupt status */ |
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224 | #define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */ |
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225 | |
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226 | /* Interrupt enable register fields */ |
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227 | #define OMAP3_TIER_MAT_IT_ENA (1 << 0) /* Enable match interrupt */ |
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228 | #define OMAP3_TIER_OVF_IT_ENA (1 << 1) /* Enable overflow interrupt */ |
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229 | #define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */ |
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230 | |
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231 | /* Timer control fields */ |
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232 | #define OMAP3_TCLR_ST (1 << 0) /* Start/stop timer */ |
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233 | #define OMAP3_TCLR_AR (1 << 1) /* Autoreload or one-shot mode */ |
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234 | #define OMAP3_TCLR_PRE (1 << 5) /* Prescaler on */ |
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235 | #define OMAP3_TCLR_PTV (1 << 1) /* looks like "bleed" from Minix */ |
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236 | #define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */ |
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237 | |
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238 | |
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239 | #define OMAP3_CM_CLKSEL_GFX 0x48004b40 |
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240 | #define OMAP3_CM_CLKEN_PLL 0x48004d00 |
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241 | #define OMAP3_CM_FCLKEN1_CORE 0x48004A00 |
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242 | #define OMAP3_CM_CLKSEL_CORE 0x48004A40 /* GPT10 src clock sel. */ |
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243 | #define OMAP3_CM_FCLKEN_PER 0x48005000 |
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244 | #define OMAP3_CM_CLKSEL_PER 0x48005040 |
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245 | #define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */ |
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246 | |
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247 | |
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248 | #define CM_MODULEMODE_MASK (0x3 << 0) |
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249 | #define CM_MODULEMODE_ENABLE (0x2 << 0) |
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250 | #define CM_MODULEMODE_DISABLED (0x0 << 0) |
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251 | |
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252 | #define CM_CLKCTRL_IDLEST (0x3 << 16) |
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253 | #define CM_CLKCTRL_IDLEST_FUNC (0x0 << 16) |
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254 | #define CM_CLKCTRL_IDLEST_TRANS (0x1 << 16) |
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255 | #define CM_CLKCTRL_IDLEST_IDLE (0x2 << 16) |
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256 | #define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16) |
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257 | |
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258 | #define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */ |
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259 | |
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260 | #define CM_WKUP_TIMER1_CLKCTRL (CM_WKUP_BASE + 0xC4) |
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261 | /* This register manages the TIMER1 clocks. [Memory Mapped] */ |
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262 | |
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263 | #define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */ |
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264 | #define CM_PER_TIMER7_CLKCTRL (CM_PER_BASE + 0x7C) |
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265 | /* This register manages the TIMER7 clocks. [Memory Mapped] */ |
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266 | |
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267 | /* CM_DPLL registers */ |
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268 | |
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269 | #define CM_DPLL_BASE 0x44E00500 /* Clock Module PLL Registers */ |
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270 | |
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271 | #define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28) |
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272 | |
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273 | #define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0) |
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274 | #define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0) |
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275 | /* Select CLK_M_OSC clock */ |
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276 | #define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0) |
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277 | /* Select CLK_32KHZ clock */ |
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278 | #define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0) |
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279 | /* Select TCLKIN clock */ |
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280 | #define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0) |
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281 | /* Select CLK_RC32K clock */ |
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282 | #define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0) |
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283 | /* Selects the CLK_32768 from 32KHz Crystal Osc */ |
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284 | |
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285 | #define CLKSEL_TIMER7_CLK (CM_DPLL_BASE + 0x04) |
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286 | #define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0) |
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287 | #define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */ |
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288 | #define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */ |
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289 | #define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */ |
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290 | #define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */ |
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291 | |
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292 | /*RTC CLOCK BASE & Registers*/ |
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293 | #define CM_RTC_BASE 0x44E00800 |
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294 | #define CM_RTC_RTC_CLKCTRL 0x0 |
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295 | #define CM_RTC_CLKSTCTRL 0x4 |
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296 | |
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297 | |
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298 | #define OMAP3_CLKSEL_GPT1 (1 << 0) |
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299 | #define OMAP3_CLKSEL_GPT10 (1 << 6) |
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300 | #define OMAP3_CLKSEL_GPT11 (1 << 7) |
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301 | |
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302 | #define OMAP34XX_CORE_L4_IO_BASE 0x48000000 |
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303 | |
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304 | #define ARM_TTBR_ADDR_MASK (0xffffc000) |
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305 | #define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/ |
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306 | #define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back */ |
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307 | #define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through */ |
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308 | #define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */ |
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309 | #define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA |
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310 | |
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311 | /* cpu control flags */ |
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312 | /* CPU control register (CP15 register 1) */ |
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313 | #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ |
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314 | #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ |
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315 | #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ |
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316 | #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ |
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317 | #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ |
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318 | #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ |
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319 | #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ |
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320 | #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ |
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321 | #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ |
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322 | #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ |
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323 | #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ |
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324 | #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ |
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325 | #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ |
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326 | #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ |
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327 | #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ |
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328 | #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ |
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329 | #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ |
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330 | #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ |
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331 | #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ |
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332 | #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ |
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333 | #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ |
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334 | #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ |
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335 | #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ |
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336 | #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ |
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337 | #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ |
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338 | #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ |
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339 | |
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340 | #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE |
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341 | |
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342 | /* VM bits */ |
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343 | |
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344 | /* Big page (1MB section) specific flags. */ |
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345 | #define ARM_VM_SECTION (1 << 1) |
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346 | /* 1MB section */ |
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347 | #define ARM_VM_SECTION_PRESENT (1 << 1) |
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348 | /* Section is present */ |
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349 | #define ARM_VM_SECTION_B (1 << 2) |
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350 | /* B Bit */ |
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351 | #define ARM_VM_SECTION_C (1 << 3) |
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352 | /* C Bit */ |
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353 | #define ARM_VM_SECTION_DOMAIN (0xF << 5) |
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354 | /* Domain Number */ |
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355 | #define ARM_VM_SECTION_SUPER (0x1 << 10) |
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356 | /* Super access only AP[1:0] */ |
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357 | #define ARM_VM_SECTION_USER (0x3 << 10) |
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358 | /* Super/User access AP[1:0] */ |
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359 | #define ARM_VM_SECTION_TEX0 (1 << 12) |
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360 | /* TEX[0] */ |
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361 | #define ARM_VM_SECTION_TEX1 (1 << 13) |
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362 | /* TEX[1] */ |
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363 | #define ARM_VM_SECTION_TEX2 (1 << 14) |
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364 | /* TEX[2] */ |
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365 | #define ARM_VM_SECTION_RO (1 << 15) |
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366 | /* Read only access AP[2] */ |
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367 | #define ARM_VM_SECTION_SHAREABLE (1 << 16) |
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368 | /* Shareable */ |
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369 | #define ARM_VM_SECTION_NOTGLOBAL (1 << 17) |
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370 | /* Not Global */ |
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371 | |
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372 | #define ARM_VM_SECTION_WB \ |
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373 | (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B ) |
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374 | /* inner and outer write-back, write-allocate */ |
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375 | #define ARM_VM_SECTION_WT \ |
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376 | (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C ) |
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377 | /* inner and outer write-through, no write-allocate */ |
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378 | #define ARM_VM_SECTION_WTWB \ |
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379 | (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C ) |
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380 | /* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */ |
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381 | |
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382 | /* shareable device */ |
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383 | #define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB |
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384 | #define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B) |
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