source: rtems/bsps/arm/include/libcpu/am335x.h @ ecf62845

Last change on this file since ecf62845 was ecf62845, checked in by Pierre-Louis Garnier <garnie_a@…>, on Feb 25, 2019 at 10:30:09 PM

arm/beagle: SPI driver

  • Property mode set to 100644
File size: 30.8 KB
Line 
1/*
2 * Copyright (c) 2012 Claas Ziemke. All rights reserved.
3 *
4 *  Claas Ziemke
5 *  Kernerstrasse 11
6 *  70182 Stuttgart
7 *  Germany
8 *  <claas.ziemke@gmx.net>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 *
14 * Modified by Ben Gras <beng@shrike-systems.com> to add lots
15 * of beagleboard/beaglebone definitions, delete lpc32xx specific
16 * ones, and merge with some other header files.
17 */
18
19#if !defined(_AM335X_H_)
20#define _AM335X_H_
21
22#define AM335X_MASK(Shift, Width) (((1 << (Width)) - 1) << (Shift))
23
24
25/* Interrupt controller memory map */
26#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
27
28/* Interrupt controller memory map */
29#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
30
31#define AM335X_INT_EMUINT             0
32    /* Emulation interrupt (EMUICINTR) */
33#define AM335X_INT_COMMTX             1
34    /* CortexA8 COMMTX */
35#define AM335X_INT_COMMRX             2
36    /* CortexA8 COMMRX */
37#define AM335X_INT_BENCH              3
38    /* CortexA8 NPMUIRQ */
39#define AM335X_INT_ELM_IRQ            4
40    /* Sinterrupt (Error location process completion) */
41#define AM335X_INT_NMI                7
42    /* nmi_int */
43#define AM335X_INT_L3DEBUG            9
44    /* l3_FlagMux_top_FlagOut1 */
45#define AM335X_INT_L3APPINT           10
46    /* l3_FlagMux_top_FlagOut0  */
47#define AM335X_INT_PRCMINT            11
48    /* irq_mpu */
49#define AM335X_INT_EDMACOMPINT        12
50    /* tpcc_int_pend_po0 */
51#define AM335X_INT_EDMAMPERR          13
52    /* tpcc_mpint_pend_po */
53#define AM335X_INT_EDMAERRINT         14
54    /* tpcc_errint_pend_po */
55#define AM335X_INT_ADC_TSC_GENINT     16
56    /* gen_intr_pend */
57#define AM335X_INT_USBSSINT           17
58    /* usbss_intr_pend */
59#define AM335X_INT_USB0               18
60    /* usb0_intr_pend */
61#define AM335X_INT_USB1               19
62    /* usb1_intr_pend */
63#define AM335X_INT_PRUSS1_EVTOUT0     20
64    /* pr1_host_intr0_intr_pend */
65#define AM335X_INT_PRUSS1_EVTOUT1     21
66    /* pr1_host_intr1_intr_pend */
67#define AM335X_INT_PRUSS1_EVTOUT2     22
68    /* pr1_host_intr2_intr_pend */
69#define AM335X_INT_PRUSS1_EVTOUT3     23
70    /* pr1_host_intr3_intr_pend */
71#define AM335X_INT_PRUSS1_EVTOUT4     24
72    /* pr1_host_intr4_intr_pend */
73#define AM335X_INT_PRUSS1_EVTOUT5     25
74    /* pr1_host_intr5_intr_pend */
75#define AM335X_INT_PRUSS1_EVTOUT6     26
76    /* pr1_host_intr6_intr_pend */
77#define AM335X_INT_PRUSS1_EVTOUT7     27
78    /* pr1_host_intr7_intr_pend */
79#define AM335X_INT_MMCSD1INT          28
80    /* MMCSD1  SINTERRUPTN */
81#define AM335X_INT_MMCSD2INT          29
82    /* MMCSD2  SINTERRUPT */
83#define AM335X_INT_I2C2INT            30
84    /* I2C2  POINTRPEND */
85#define AM335X_INT_eCAP0INT           31
86    /* ecap_intr_intr_pend */
87#define AM335X_INT_GPIOINT2A          32
88    /* GPIO 2  POINTRPEND1 */
89#define AM335X_INT_GPIOINT2B          33
90    /* GPIO 2  POINTRPEND2 */
91#define AM335X_INT_USBWAKEUP          34
92    /* USBSS  slv0p_Swakeup */
93#define AM335X_INT_LCDCINT            36
94    /* LCDC  lcd_irq */
95#define AM335X_INT_GFXINT             37
96    /* SGX530  THALIAIRQ */
97#define AM335X_INT_ePWM2INT           39
98    /* (PWM Subsystem)  epwm_intr_intr_pend */
99#define AM335X_INT_3PGSWRXTHR0        40
100    /* (Ethernet)  c0_rx_thresh_pend (RX_THRESH_PULSE) */
101#define AM335X_INT_3PGSWRXINT0        41
102    /* CPSW (Ethernet)  c0_rx_pend */
103#define AM335X_INT_3PGSWTXINT0        42
104    /* CPSW (Ethernet)  c0_tx_pend */
105#define AM335X_INT_3PGSWMISC0         43
106    /* CPSW (Ethernet)  c0_misc_pend */
107#define AM335X_INT_UART3INT           44
108    /* UART3  niq */
109#define AM335X_INT_UART4INT           45
110    /* UART4  niq */
111#define AM335X_INT_UART5INT           46
112    /* UART5  niq */
113#define AM335X_INT_eCAP1INT           47
114    /* (PWM Subsystem)  ecap_intr_intr_pend */
115#define AM335X_INT_DCAN0_INT0         52
116    /* DCAN0  dcan_intr0_intr_pend */
117#define AM335X_INT_DCAN0_INT1         53
118    /* DCAN0  dcan_intr1_intr_pend */
119#define AM335X_INT_DCAN0_PARITY       54
120    /* DCAN0  dcan_uerr_intr_pend */
121#define AM335X_INT_DCAN1_INT0         55
122    /* DCAN1  dcan_intr0_intr_pend */
123#define AM335X_INT_DCAN1_INT1         56
124    /* DCAN1  dcan_intr1_intr_pend */
125#define AM335X_INT_DCAN1_PARITY       57
126    /* DCAN1  dcan_uerr_intr_pend */
127#define AM335X_INT_ePWM0_TZINT        58
128    /* eHRPWM0 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
129#define AM335X_INT_ePWM1_TZINT        59
130    /* eHRPWM1 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
131#define AM335X_INT_ePWM2_TZINT        60
132    /* eHRPWM2 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
133#define AM335X_INT_eCAP2INT           61
134    /* eCAP2 (PWM Subsystem)  ecap_intr_intr_pend */
135#define AM335X_INT_GPIOINT3A          62
136    /* GPIO 3  POINTRPEND1 */
137#define AM335X_INT_GPIOINT3B          63
138    /* GPIO 3  POINTRPEND2 */
139#define AM335X_INT_MMCSD0INT          64
140    /* MMCSD0  SINTERRUPTN */
141#define AM335X_INT_SPI0INT            65
142    /* McSPI0  SINTERRUPTN */
143#define AM335X_INT_TINT0              66
144    /* Timer0  POINTR_PEND */
145#define AM335X_INT_TINT1_1MS          67
146    /* DMTIMER_1ms  POINTR_PEND */
147#define AM335X_INT_TINT2              68
148    /* DMTIMER2  POINTR_PEND */
149#define AM335X_INT_TINT3              69
150    /* DMTIMER3  POINTR_PEND */
151#define AM335X_INT_I2C0INT            70
152    /* I2C0  POINTRPEND */
153#define AM335X_INT_I2C1INT            71
154    /* I2C1  POINTRPEND */
155#define AM335X_INT_UART0INT           72
156    /* UART0  niq */
157#define AM335X_INT_UART1INT           73
158    /* UART1  niq */
159#define AM335X_INT_UART2INT           74
160    /* UART2  niq */
161#define AM335X_INT_RTCINT             75
162    /* RTC  timer_intr_pend */
163#define AM335X_INT_RTCALARMINT        76
164    /* RTC  alarm_intr_pend */
165#define AM335X_INT_MBINT0             77
166    /* Mailbox0 (mail_u0_irq)  initiator_sinterrupt_q_n */
167#define AM335X_INT_M3_TXEV            78
168    /* Wake M3 Subsystem  TXEV */
169#define AM335X_INT_eQEP0INT           79
170    /* eQEP0 (PWM Subsystem)  eqep_intr_intr_pend */
171#define AM335X_INT_MCATXINT0          80
172    /* McASP0  mcasp_x_intr_pend */
173#define AM335X_INT_MCARXINT0          81
174    /* McASP0  mcasp_r_intr_pend */
175#define AM335X_INT_MCATXINT1          82
176    /* McASP1  mcasp_x_intr_pend */
177#define AM335X_INT_MCARXINT1          83
178    /* McASP1  mcasp_r_intr_pend */
179#define AM335X_INT_ePWM0INT           86
180    /* (PWM Subsystem)  epwm_intr_intr_pend */
181#define AM335X_INT_ePWM1INT           87
182    /* (PWM Subsystem)  epwm_intr_intr_pend */
183#define AM335X_INT_eQEP1INT           88
184    /* (PWM Subsystem)  eqep_intr_intr_pend */
185#define AM335X_INT_eQEP2INT           89
186    /* (PWM Subsystem)  eqep_intr_intr_pend */
187#define AM335X_INT_DMA_INTR_PIN2      90
188    /* External DMA/Interrupt Pin2  */
189#define AM335X_INT_WDT1INT            91
190    /* (Public Watchdog) WDTIMER1 PO_INT_PEND */
191#define AM335X_INT_TINT4              92
192    /* DMTIMER4  POINTR_PEN */
193#define AM335X_INT_TINT5              93
194    /* DMTIMER5  POINTR_PEN */
195#define AM335X_INT_TINT6              94
196    /* DMTIMER6  POINTR_PEND */
197#define AM335X_INT_TINT7              95
198    /* DMTIMER7  POINTR_PEND */
199#define AM335X_INT_GPIOINT0A          96
200    /* GPIO 0  POINTRPEND1 */
201#define AM335X_INT_GPIOINT0B          97
202    /* GPIO 0  POINTRPEND2 */
203#define AM335X_INT_GPIOINT1A          98
204    /* GPIO 1  POINTRPEND1 */
205#define AM335X_INT_GPIOINT1B          99
206    /* GPIO 1  POINTRPEND2 */
207#define AM335X_INT_GPMCINT            100
208    /* GPMC  gpmc_sinterrupt */
209#define AM335X_INT_DDRERR0            101
210    /* EMIF  sys_err_intr_pend */
211#define AM335X_INT_TCERRINT0          112
212    /* TPTC0  tptc_erint_pend_po */
213#define AM335X_INT_TCERRINT1          113
214    /* TPTC1  tptc_erint_pend_po */
215#define AM335X_INT_TCERRINT2          114
216    /* TPTC2  tptc_erint_pend_po */
217#define AM335X_INT_ADC_TSC_PENINT     115
218    /* ADC_TSC  pen_intr_pend */
219#define AM335X_INT_SMRFLX_Sabertooth  120
220    /* Smart Reflex 0  intrpen */
221#define AM335X_INT_SMRFLX_Core        121
222    /* Smart Reflex 1  intrpend */
223#define AM335X_INT_DMA_INTR_PIN0      123
224    /* pi_x_dma_event_intr0 (xdma_event_intr0) */
225#define AM335X_INT_DMA_INTR_PIN1      124
226    /* pi_x_dma_event_intr1 (xdma_event_intr1) */
227#define AM335X_INT_SPI1INT            125
228    /* McSPI1  SINTERRUPTN */
229
230#define OMAP3_AM335X_NR_IRQ_VECTORS    125
231
232#define AM335X_DMTIMER0_BASE      0x44E05000
233    /* DMTimer0 Registers */
234#define AM335X_DMTIMER1_1MS_BASE  0x44E31000
235    /* DMTimer1 1ms Registers (Accurate 1ms timer) */
236#define AM335X_DMTIMER2_BASE      0x48040000
237    /*  DMTimer2 Registers */
238#define AM335X_DMTIMER3_BASE      0x48042000
239    /*  DMTimer3 Registers */
240#define AM335X_DMTIMER4_BASE      0x48044000
241    /* DMTimer4 Registers  */
242#define AM335X_DMTIMER5_BASE      0x48046000
243    /* DMTimer5 Registers  */
244#define AM335X_DMTIMER6_BASE      0x48048000
245    /*  DMTimer6 Registers */
246#define AM335X_DMTIMER7_BASE      0x4804A000
247    /*  DMTimer7 Registers */
248
249/* General-purpose timer registers
250   AM335x non 1MS timers have different offsets */
251#define AM335X_TIMER_TIDR             0x000
252    /* IP revision code */
253#define AM335X_TIMER_TIOCP_CFG        0x010
254    /* Controls params for GP timer L4 interface */
255#define AM335X_TIMER_IRQSTATUS_RAW    0x024
256    /* Timer IRQSTATUS Raw Register */
257#define AM335X_TIMER_IRQSTATUS        0x028
258    /* Timer IRQSTATUS Register */
259#define AM335X_TIMER_IRQENABLE_SET    0x02C
260    /* Timer IRQENABLE Set Register */
261#define AM335X_TIMER_IRQENABLE_CLR    0x030
262    /* Timer IRQENABLE Clear Register */
263#define AM335X_TIMER_IRQWAKEEN        0x034
264    /* Timer IRQ Wakeup Enable Register */
265#define AM335X_TIMER_TCLR             0x038
266    /* Controls optional features */
267#define AM335X_TIMER_TCRR             0x03C
268    /* Internal counter value */
269#define AM335X_TIMER_TLDR             0x040
270    /* Timer load value */
271#define AM335X_TIMER_TTGR             0x044
272    /* Triggers counter reload */
273#define AM335X_TIMER_TWPS             0x048
274    /* Indicates if Write-Posted pending */
275#define AM335X_TIMER_TMAR             0x04C
276    /* Value to be compared with counter */
277#define AM335X_TIMER_TCAR1            0x050
278    /* First captured value of counter register */
279#define AM335X_TIMER_TSICR            0x054
280    /* Control posted mode and functional SW reset */
281#define AM335X_TIMER_TCAR2            0x058
282    /* Second captured value of counter register */
283#define AM335X_WDT_BASE                0x44E35000
284    /* Watchdog timer */
285#define AM335X_WDT_WWPS                0x34
286    /* Command posted status */
287#define AM335X_WDT_WSPR                0x48
288    /* Activate/deactivate sequence */
289
290/* RTC registers */
291#define AM335X_RTC_BASE         0x44E3E000
292#define AM335X_RTC_SECS         0x0
293#define AM335X_RTC_MINS         0x4
294#define AM335X_RTC_HOURS        0x8
295#define AM335X_RTC_DAYS         0xc
296#define AM335X_RTC_MONTHS       0x10
297#define AM335X_RTC_YEARS        0x14
298#define AM335X_RTC_WEEKS        0x18
299#define AM335X_RTC_CTRL_REG     0x40
300#define AM335X_RTC_STATUS_REG   0x44
301#define AM335X_RTC_REV_REG      0x74
302#define AM335X_RTC_SYSCONFIG    0x78
303#define AM335X_RTC_KICK0        0x6c
304#define AM335X_RTC_KICK1        0x70
305#define AM335X_RTC_OSC_CLOCK    0x54
306
307#define AM335X_RTC_KICK0_KEY    0x83E70B13
308#define AM335X_RTC_KICK1_KEY    0x95A4F1E0
309
310/* GPIO memory-mapped registers */
311
312#define AM335X_GPIO0_BASE           0x44E07000
313    /* GPIO Bank 0 base Register */
314#define AM335X_GPIO1_BASE           0x4804C000
315    /* GPIO Bank 1 base Register */
316#define AM335X_GPIO2_BASE           0x481AC000
317    /* GPIO Bank 2 base Register */
318#define AM335X_GPIO3_BASE           0x481AE000
319    /* GPIO Bank 3 base Register */
320
321#define AM335X_GPIO_REVISION        0x00
322#define AM335X_GPIO_SYSCONFIG       0x10
323#define AM335X_GPIO_EOI             0x20
324#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24
325#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28
326#define AM335X_GPIO_IRQSTATUS_0     0x2C
327#define AM335X_GPIO_IRQSTATUS_1     0x30
328#define AM335X_GPIO_IRQSTATUS_SET_0 0x34
329#define AM335X_GPIO_IRQSTATUS_SET_1 0x38
330#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C
331#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40
332#define AM335X_GPIO_IRQWAKEN_0      0x44
333#define AM335X_GPIO_IRQWAKEN_1      0x48
334#define AM335X_GPIO_SYSSTATUS       0x114
335#define AM335X_GPIO_CTRL            0x130
336#define AM335X_GPIO_OE              0x134
337#define AM335X_GPIO_DATAIN          0x138
338#define AM335X_GPIO_DATAOUT         0x13C
339#define AM335X_GPIO_LEVELDETECT0    0x140
340#define AM335X_GPIO_LEVELDETECT1    0x144
341#define AM335X_GPIO_RISINGDETECT    0x148
342#define AM335X_GPIO_FALLINGDETECT   0x14C
343#define AM335X_GPIO_DEBOUNCENABLE   0x150
344#define AM335X_GPIO_DEBOUNCINGTIME  0x154
345#define AM335X_GPIO_CLEARDATAOUT    0x190
346#define AM335X_GPIO_SETDATAOUT      0x194
347
348/* AM335X Pad Configuration Register Base */
349#define AM335X_PADCONF_BASE 0x44E10000
350
351/* Memory mapped register offset for Control Module */
352#define AM335X_CONF_GPMC_AD0 0x800
353#define AM335X_CONF_GPMC_AD1 0x804
354#define AM335X_CONF_GPMC_AD2 0x808
355#define AM335X_CONF_GPMC_AD3 0x80C
356#define AM335X_CONF_GPMC_AD4 0x810
357#define AM335X_CONF_GPMC_AD5 0x814
358#define AM335X_CONF_GPMC_AD6 0x818
359#define AM335X_CONF_GPMC_AD7 0x81C
360#define AM335X_CONF_GPMC_AD8 0x820
361#define AM335X_CONF_GPMC_AD9 0x824
362#define AM335X_CONF_GPMC_AD10 0x828
363#define AM335X_CONF_GPMC_AD11 0x82C
364#define AM335X_CONF_GPMC_AD12 0x830
365#define AM335X_CONF_GPMC_AD13 0x834
366#define AM335X_CONF_GPMC_AD14 0x838
367#define AM335X_CONF_GPMC_AD15 0x83C
368#define AM335X_CONF_GPMC_A0 0x840
369#define AM335X_CONF_GPMC_A1 0x844
370#define AM335X_CONF_GPMC_A2 0x848
371#define AM335X_CONF_GPMC_A3 0x84C
372#define AM335X_CONF_GPMC_A4 0x850
373#define AM335X_CONF_GPMC_A5 0x854
374#define AM335X_CONF_GPMC_A6 0x858
375#define AM335X_CONF_GPMC_A7 0x85C
376#define AM335X_CONF_GPMC_A8 0x860
377#define AM335X_CONF_GPMC_A9 0x864
378#define AM335X_CONF_GPMC_A10 0x868
379#define AM335X_CONF_GPMC_A11 0x86C
380#define AM335X_CONF_GPMC_WAIT0 0x870
381#define AM335X_CONF_GPMC_WPN 0x874
382#define AM335X_CONF_GPMC_BEN1 0x878
383#define AM335X_CONF_GPMC_CSN0 0x87C
384#define AM335X_CONF_GPMC_CSN1 0x880
385#define AM335X_CONF_GPMC_CSN2 0x884
386#define AM335X_CONF_GPMC_CSN3 0x888
387#define AM335X_CONF_GPMC_CLK 0x88C
388#define AM335X_CONF_GPMC_ADVN_ALE 0x890
389#define AM335X_CONF_GPMC_OEN_REN 0x894
390#define AM335X_CONF_GPMC_WEN 0x898
391#define AM335X_CONF_GPMC_BEN0_CLE 0x89C
392#define AM335X_CONF_LCD_DATA0 0x8A0
393#define AM335X_CONF_LCD_DATA1 0x8A4
394#define AM335X_CONF_LCD_DATA2 0x8A8
395#define AM335X_CONF_LCD_DATA3 0x8AC
396#define AM335X_CONF_LCD_DATA4 0x8B0
397#define AM335X_CONF_LCD_DATA5 0x8B4
398#define AM335X_CONF_LCD_DATA6 0x8B8
399#define AM335X_CONF_LCD_DATA7 0x8BC
400#define AM335X_CONF_LCD_DATA8 0x8C0
401#define AM335X_CONF_LCD_DATA9 0x8C4
402#define AM335X_CONF_LCD_DATA10 0x8C8
403#define AM335X_CONF_LCD_DATA11 0x8CC
404#define AM335X_CONF_LCD_DATA12 0x8D0
405#define AM335X_CONF_LCD_DATA13 0x8D4
406#define AM335X_CONF_LCD_DATA14 0x8D8
407#define AM335X_CONF_LCD_DATA15 0x8DC
408#define AM335X_CONF_LCD_VSYNC 0x8E0
409#define AM335X_CONF_LCD_HSYNC 0x8E4
410#define AM335X_CONF_LCD_PCLK 0x8E8
411#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC
412#define AM335X_CONF_MMC0_DAT3 0x8F0
413#define AM335X_CONF_MMC0_DAT2 0x8F4
414#define AM335X_CONF_MMC0_DAT1 0x8F8
415#define AM335X_CONF_MMC0_DAT0 0x8FC
416#define AM335X_CONF_MMC0_CLK 0x900
417#define AM335X_CONF_MMC0_CMD 0x904
418#define AM335X_CONF_MII1_COL 0x908
419#define AM335X_CONF_MII1_CRS 0x90C
420#define AM335X_CONF_MII1_RX_ER 0x910
421#define AM335X_CONF_MII1_TX_EN 0x914
422#define AM335X_CONF_MII1_RX_DV 0x918
423#define AM335X_CONF_MII1_TXD3 0x91C
424#define AM335X_CONF_MII1_TXD2 0x920
425#define AM335X_CONF_MII1_TXD1 0x924
426#define AM335X_CONF_MII1_TXD0 0x928
427#define AM335X_CONF_MII1_TX_CLK 0x92C
428#define AM335X_CONF_MII1_RX_CLK 0x930
429#define AM335X_CONF_MII1_RXD3 0x934
430#define AM335X_CONF_MII1_RXD2 0x938
431#define AM335X_CONF_MII1_RXD1 0x93C
432#define AM335X_CONF_MII1_RXD0 0x940
433#define AM335X_CONF_RMII1_REF_CLK 0x944
434#define AM335X_CONF_MDIO 0x948
435#define AM335X_CONF_MDC 0x94C
436#define AM335X_CONF_SPI0_SCLK 0x950
437#define AM335X_CONF_SPI0_D0 0x954
438#define AM335X_CONF_SPI0_D1 0x958
439#define AM335X_CONF_SPI0_CS0 0x95C
440#define AM335X_CONF_SPI0_CS1 0x960
441#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964
442#define AM335X_CONF_UART0_CTSN 0x968
443#define AM335X_CONF_UART0_RTSN 0x96C
444#define AM335X_CONF_UART0_RXD 0x970
445#define AM335X_CONF_UART0_TXD 0x974
446#define AM335X_CONF_UART1_CTSN 0x978
447#define AM335X_CONF_UART1_RTSN 0x97C
448#define AM335X_CONF_UART1_RXD 0x980
449#define AM335X_CONF_UART1_TXD 0x984
450#define AM335X_CONF_I2C0_SDA 0x988
451#define AM335X_CONF_I2C0_SCL 0x98C
452#define AM335X_CONF_MCASP0_ACLKX 0x990
453#define AM335X_CONF_MCASP0_FSX 0x994
454#define AM335X_CONF_MCASP0_AXR0 0x998
455#define AM335X_CONF_MCASP0_AHCLKR 0x99C
456#define AM335X_CONF_MCASP0_ACLKR 0x9A0
457#define AM335X_CONF_MCASP0_FSR 0x9A4
458#define AM335X_CONF_MCASP0_AXR1 0x9A8
459#define AM335X_CONF_MCASP0_AHCLKX 0x9AC
460#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0
461#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4
462#define AM335X_CONF_WARMRSTN 0x9B8
463#define AM335X_CONF_NNMI 0x9C0
464#define AM335X_CONF_TMS 0x9D0
465#define AM335X_CONF_TDI 0x9D4
466#define AM335X_CONF_TDO 0x9D8
467#define AM335X_CONF_TCK 0x9DC
468#define AM335X_CONF_TRSTN 0x9E0
469#define AM335X_CONF_EMU0 0x9E4
470#define AM335X_CONF_EMU1 0x9E8
471#define AM335X_CONF_RTC_PWRONRSTN 0x9F8
472#define AM335X_CONF_PMIC_POWER_EN 0x9FC
473#define AM335X_CONF_EXT_WAKEUP 0xA00
474#define AM335X_CONF_RTC_KALDO_ENN 0xA04
475#define AM335X_CONF_USB0_DRVVBUS 0xA1C
476#define AM335X_CONF_USB1_DRVVBUS 0xA34
477
478/* Registers for PWM Subsystem */
479#define AM335X_PWMSS_CTRL      (0x664)
480#define AM335X_CM_PER_EPWMSS0_CLKCTRL    (0xD4)
481#define AM335X_CM_PER_EPWMSS1_CLKCTRL    (0xCC)
482#define AM335X_CM_PER_EPWMSS2_CLKCTRL    (0xD8)
483#define AM335X_CONTROL_MODULE      (0x44e10000)
484#define AM335X_CM_PER_ADDR     (0x44e00000)
485#define AM335X_PWMSS_CLKSTATUS         (0xC)
486#define AM335X_PWMSS0_MMAP_ADDR        0x48300000
487#define AM335X_PWMSS1_MMAP_ADDR        0x48302000
488#define AM335X_PWMSS2_MMAP_ADDR        0x48304000
489#define AM335X_PWMSS_MMAP_LEN          0x1000
490#define AM335X_PWMSS_IDVER         0x0
491#define AM335X_PWMSS_SYSCONFIG     0x4
492#define AM335X_PWMSS_CLKCONFIG     0x8
493#define AM335X_PWMSS_CLK_EN_ACK        0x100
494#define AM335X_EPWM_TBCTL          0x0
495#define AM335X_EPWM_TBSTS          0x2
496#define AM335X_EPWM_TBPHSHR        0x4
497#define AM335X_EPWM_TBPHS          0x6
498#define AM335X_EPWM_TBCNT          0x8
499#define AM335X_EPWM_TBPRD          0xA
500#define AM335X_EPWM_CMPCTL         0xE
501#define AM335X_EPWM_CMPAHR         0x10
502#define AM335X_EPWM_CMPA           0x12
503#define AM335X_EPWM_CMPB           0x14
504#define AM335X_EPWM_AQCTLA         0x16
505#define AM335X_EPWM_AQCTLB         0x18
506#define AM335X_EPWM_AQSFRC         0x1A
507#define AM335X_EPWM_AQCSFRC        0x1C
508#define AM335X_EPWM_DBCTL          0x1E
509#define AM335X_EPWM_DBRED          0x20
510#define AM335X_EPWM_DBFED          0x22
511#define AM335X_TBCTL_CTRMODE_UP        0x0
512#define AM335X_TBCTL_CTRMODE_DOWN      0x1
513#define AM335X_TBCTL_CTRMODE_UPDOWN    0x2
514#define AM335X_TBCTL_CTRMODE_FREEZE    0x3
515#define AM335X_EPWM_AQCTLA_ZRO_XALOW         (0x0001u)
516#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH        (0x0002u)
517#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE   (0x0003u)
518#define AM335X_EPWM_AQCTLA_CAU_SHIFT          (0x0004u)
519#define AM335X_EPWM_AQCTLA_ZRO_XBLOW         (0x0001u)
520#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH        (0x0002u)
521#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE   (0x0003u)
522#define AM335X_EPWM_AQCTLB_CBU_SHIFT          (0x0008u)
523#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE  (0x0003u)
524#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN      (0x00000001u)
525#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN      (0x00000002u)
526#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN      (0x00000004u)
527#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
528#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
529#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
530#define AM335X_TBCTL_CLKDIV_MASK              (3 << 10)
531#define AM335X_TBCTL_HSPCLKDIV_MASK           (3 << 7)
532#define AM335X_EPWM_TBCTL_CLKDIV              (0x1C00u)
533#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT        (0x000Au)
534#define AM335X_EPWM_TBCTL_HSPCLKDIV           (0x0380u)
535#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT     (0x0007u)
536#define AM335X_EPWM_TBCTL_PRDLD               (0x0008u)
537#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK      AM335X_EPWM_TBCTL_PRDLD
538#define AM335X_EPWM_SHADOW_WRITE_ENABLE       0x0
539#define AM335X_EPWM_SHADOW_WRITE_DISABLE      0x1
540#define AM335X_EPWM_TBCTL_PRDLD_SHIFT         (0x0003u)
541#define AM335X_EPWM_TBCTL_CTRMODE             (0x0003u)
542#define AM335X_EPWM_COUNTER_MODE_MASK         AM335X_EPWM_TBCTL_CTRMODE
543#define AM335X_TBCTL_FREERUN                  (2 << 14)
544#define AM335X_TBCTL_CTRMODE_SHIFT            (0x0000u)
545#define AM335X_EPWM_COUNT_UP                  (AM335X_TBCTL_CTRMODE_UP << \
546                                                     AM335X_TBCTL_CTRMODE_SHIFT)
547
548#define AM335X_EPWM_REGS                       (0x00000200)
549#define AM335X_EPWM_0_REGS                     (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS)
550#define AM335X_EPWM_1_REGS                     (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS)
551#define AM335X_EPWM_2_REGS                     (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS)
552
553#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE   (0x00000003u)
554#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC  (0x0u)
555#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
556#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST       (0x00030000u)
557
558#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE   (0x00000003u)
559#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST       (0x00030000u)
560#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC  (0x0u)
561#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
562
563#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE   (0x00000003u)
564#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC  (0x0u)
565#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
566#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST       (0x00030000u)
567
568
569
570/* I2C registers */
571#define AM335X_I2C0_BASE 0x44e0b000
572    /* I2C0 base address */
573#define AM335X_I2C1_BASE 0x4802a000
574    /* I2C1 base address */
575#define AM335X_I2C2_BASE 0x4819c000
576    /* I2C2 base address */
577#define AM335X_I2C_REVNB_LO        0x00
578    /* Module Revision Register (low bytes) */
579#define AM335X_I2C_REVNB_HI        0x04
580    /* Module Revision Register (high bytes) */
581#define AM335X_I2C_SYSC            0x10
582    /* System Configuration Register */
583#define AM335X_I2C_IRQSTATUS_RAW   0x24
584    /* I2C Status Raw Register */
585#define AM335X_I2C_IRQSTATUS       0x28
586    /* I2C Status Register */
587#define AM335X_I2C_IRQENABLE_SET   0x2c
588    /* I2C Interrupt Enable Set Register */
589#define AM335X_I2C_IRQENABLE_CLR   0x30
590    /* I2C Interrupt Enable Clear Register */
591#define AM335X_I2C_WE              0x34
592    /* I2C Wakeup Enable Register */
593#define AM335X_I2C_DMARXENABLE_SET 0x38
594    /* Receive DMA Enable Set Register */
595#define AM335X_I2C_DMATXENABLE_SET 0x3c
596    /* Transmit DMA Enable Set Register */
597#define AM335X_I2C_DMARXENABLE_CLR 0x40
598    /* Receive DMA Enable Clear Register */
599#define AM335X_I2C_DMATXENABLE_CLR 0x44
600    /* Transmit DMA Enable Clear Register */
601#define AM335X_I2C_DMARXWAKE_EN    0x48
602    /* Receive DMA Wakeup Register */
603#define AM335X_I2C_DMATXWAKE_EN    0x4c
604    /* Transmit DMA Wakeup Register */
605#define AM335X_I2C_SYSS            0x90
606    /* System Status Register */
607#define AM335X_I2C_BUF             0x94
608    /* Buffer Configuration Register */
609#define AM335X_I2C_CNT             0x98
610    /* Data Counter Register */
611#define AM335X_I2C_DATA            0x9c
612    /* Data Access Register */
613#define AM335X_I2C_CON             0xa4
614    /* I2C Configuration Register */
615#define AM335X_I2C_OA              0xa8
616    /* I2C Own Address Register */
617#define AM335X_I2C_SA              0xac
618    /* I2C Slave Address Register */
619#define AM335X_I2C_PSC             0xb0
620    /* I2C Clock Prescaler Register */
621#define AM335X_I2C_SCLL            0xb4
622    /* I2C SCL Low Time Register */
623#define AM335X_I2C_SCLH            0xb8
624    /* I2C SCL High Time Register */
625#define AM335X_I2C_SYSTEST         0xbc
626    /* System Test Register */
627#define AM335X_I2C_BUFSTAT         0xc0
628    /* I2C Buffer Status Register */
629#define AM335X_I2C_OA1             0xc4
630    /* I2C Own Address 1 Register */
631#define AM335X_I2C_OA2             0xc8
632    /* I2C Own Address 2 Register */
633#define AM335X_I2C_OA3             0xcc
634    /* I2C Own Address 3 Register */
635#define AM335X_I2C_ACTOA           0xd0
636    /* Active Own Address Register */
637#define AM335X_I2C_SBLOCK          0xd4
638    /* I2C Clock Blocking Enable Register */
639
640#define AM335X_CM_PER_L4LS_CLKSTCTRL  (0x0)
641#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP  (0x2u)
642#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL  (0x00000003u)
643#define AM335X_CM_PER_L4LS_CLKCTRL  (0x60)
644#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
645#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE  (0x00000003u)
646#define AM335X_CM_PER_I2C1_CLKCTRL  (0x48)
647#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
648#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE  (0x00000003u)
649#define AM335X_CM_PER_I2C2_CLKCTRL (0x44)
650#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
651#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE  (0x00000003u)
652#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
653#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u)
654#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE   (0x00000003u)
655#define AM335X_CM_PER_SPI0_CLKCTRL (0x4c)
656#define AM335X_CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
657#define AM335X_CM_PER_SPI0_CLKCTRL_MODULEMODE  (0x00000003u)
658#define AM335X_I2C_CON_XSA  (0x00000100u)
659#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR  AM335X_I2C_CON_XSA
660#define AM335X_I2C_CON_XSA_SHIFT  (0x00000008u)
661#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR  (0 << AM335X_I2C_CON_XSA_SHIFT)
662#define AM335X_I2C_CON_I2C_EN   (0x00008000u)
663#define AM335X_I2C_CON_TRX   (0x00000200u)
664#define AM335X_I2C_CON_MST   (0x00000400u)
665#define AM335X_I2C_CON_STB   (0x00000800u)
666#define AM335X_I2C_SYSC_AUTOIDLE   (0x00000001u)
667
668/*I2C0 module clock registers*/
669#define AM335X_CM_WKUP_CONTROL_CLKCTRL   (0x4)
670#define AM335X_CM_WKUP_CLKSTCTRL   (0x0)
671#define AM335X_CM_WKUP_I2C0_CLKCTRL   (0xb8)
672#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
673#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE   (0x00000003u)
674#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC   (0x0u)
675#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
676#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST   (0x00030000u)
677#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK   (0x00000800u)
678#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC   (0x0u)
679#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
680#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST   (0x00030000u)
681#define AM335X_SOC_CM_WKUP_REGS                     (AM335X_CM_PER_ADDR + 0x400)
682
683/* SPI0 module clock registers */
684#define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST_FUNC   (0x0u)
685#define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
686#define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST   (0x00030000u)
687
688
689/* I2C status Register */
690#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
691#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
692#define AM335X_I2C_IRQSTATUS_AL   (1<<0)
693#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
694#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
695#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
696#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
697#define AM335X_I2C_BUF_TXFIFO_CLR   (0x00000040u)
698#define AM335X_I2C_BUF_RXFIFO_CLR   (0x00004000u)
699#define AM335X_I2C_IRQSTATUS_AAS  (1 << 9)
700#define AM335X_I2C_IRQSTATUS_BF  (1 << 8)
701#define AM335X_I2C_IRQSTATUS_STC  (1 << 6)
702#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
703#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
704#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
705
706#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
707#define AM335X_I2C_CON_STOP  (0x00000002u)
708#define AM335X_I2C_CON_START (0x00000001u)
709#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
710#define AM335X_I2C_CFG_MST_TX  (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
711#define AM335X_I2C_IRQSTATUS_RAW_BB   (0x00001000u)
712#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
713#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
714
715
716/* SPI registers */
717#define AM335X_SPI0_BASE 0x48030000
718    /* SPI0 base address */
719#define AM335X_SPI1_BASE 0x481A0000
720    /* SPI1 base address */
721
722#define AM335X_SPI_REVISION         0x000
723#define AM335X_SPI_SYSCONFIG        0x110
724#define AM335X_SPI_SYSSTATUS        0x114
725#define AM335X_SPI_IRQSTATUS        0x118
726#define AM335X_SPI_IRQENABLE        0x11c
727#define AM335X_SPI_WAKEUPENABLE     0x120
728#define AM335X_SPI_SYST             0x124
729#define AM335X_SPI_MODULCTRL        0x128
730#define AM335X_SPI_CH0CONF          0x12c
731#define AM335X_SPI_CH0STAT          0x130
732#define AM335X_SPI_CH0CTRL          0x134
733#define AM335X_SPI_TX0              0x138
734#define AM335X_SPI_RX0              0x13C
735#define AM335X_SPI_XFERLEVEL        0x17c
736
737/* SPI sysconfig Register */
738#define AM335X_SPI_SYSCONFIG_SOFTRESET (1 << 1)
739
740/* SPI sysstatus Register */
741#define AM335X_SPI_SYSSTATUS_RESETDONE (1 << 0)
742
743/* SPI interrupt status Register */
744#define AM335X_SPI_IRQSTATUS_TX0_EMPTY (1 << 0)
745#define AM335X_SPI_IRQSTATUS_RX0_FULL  (1 << 2)
746
747/* SPI interrupt enable Register */
748#define AM335X_SPI_IRQENABLE_TX0_EMPTY (1 << 0)
749#define AM335X_SPI_IRQENABLE_RX0_FULL  (1 << 2)
750
751/* SPI system Register */
752#define AM335X_SPI_SYST_SPIEN_0     (1 << 0)
753#define AM335X_SPI_SYST_SPIDAT_0    (1 << 4)
754#define AM335X_SPI_SYST_SPIDAT_1    (1 << 5)
755#define AM335X_SPI_SYST_SPIDATDIR0  (1 << 8)
756#define AM335X_SPI_SYST_SPIDATDIR1  (1 << 9)
757#define AM335X_SPI_SYST_SSB         (1 << 11)
758
759/* SPI modulctrl Register */
760#define AM335X_SPI_MODULCTRL_SINGLE (1 << 0)
761#define AM335X_SPI_MODULCTRL_PIN34  (1 << 1)
762#define AM335X_SPI_MODULCTRL_MS     (1 << 2)
763
764/* SPI Channel 0 Configuration Register */
765#define AM335X_SPI_CH0CONF_PHA      (1 << 0)
766#define AM335X_SPI_CH0CONF_POL      (1 << 1)
767#define AM335X_SPI_CH0CONF_CLKD_SHIFT 2
768#define AM335X_SPI_CH0CONF_CLKD_WIDTH 4
769#define AM335X_SPI_CH0CONF_CLKD_MASK AM335X_MASK(AM335X_SPI_CH0CONF_CLKD_SHIFT, AM335X_SPI_CH0CONF_CLKD_WIDTH)
770#define AM335X_SPI_CH0CONF_CLKD(X) (((X) << AM335X_SPI_CH0CONF_CLKD_SHIFT) & AM335X_SPI_CH0CONF_CLKD_MASK)
771#define AM335X_SPI_CH0CONF_EPOL     (1 << 6)
772#define AM335X_SPI_CH0CONF_WL_SHIFT 7
773#define AM335X_SPI_CH0CONF_WL_WIDTH 5
774#define AM335X_SPI_CH0CONF_WL_MASK AM335X_MASK(AM335X_SPI_CH0CONF_WL_SHIFT, AM335X_SPI_CH0CONF_WL_WIDTH)
775#define AM335X_SPI_CH0CONF_WL(X) (((X) << AM335X_SPI_CH0CONF_WL_SHIFT) & AM335X_SPI_CH0CONF_WL_MASK)
776#define AM335X_SPI_CH0CONF_TRM_SHIFT 12
777#define AM335X_SPI_CH0CONF_TRM_WIDTH 2
778#define AM335X_SPI_CH0CONF_TRM_MASK AM335X_MASK(AM335X_SPI_CH0CONF_TRM_SHIFT, AM335X_SPI_CH0CONF_TRM_WIDTH)
779#define AM335X_SPI_CH0CONF_TRM(X) (((X) << AM335X_SPI_CH0CONF_TRM_SHIFT) & AM335X_SPI_CH0CONF_TRM_MASK)
780#define AM335X_SPI_CH0CONF_DPE0     (1 << 16)
781#define AM335X_SPI_CH0CONF_DPE1     (1 << 17)
782#define AM335X_SPI_CH0CONF_IS       (1 << 18)
783#define AM335X_SPI_CH0CONF_FORCE    (1 << 20)
784#define AM335X_SPI_CH0CONF_SBPOL    (1 << 27)
785#define AM335X_SPI_CH0CONF_FFEW     (1 << 27)
786#define AM335X_SPI_CH0CONF_FFER     (1 << 28)
787
788/* SPI Channel 0 Status Register */
789#define AM335X_SPI_CH0STAT_RXS      (1 << 0)
790#define AM335X_SPI_CH0STAT_TXS      (1 << 1)
791
792/* SPI Channel 0 Control Register */
793#define AM335X_SPI_CH0CTRL_EN       (1 << 0)
794
795#endif
Note: See TracBrowser for help on using the repository browser.