1 | /**************************************************************************//**
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2 | * @file |
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3 | * @brief CMSIS Cortex-M Core Function/Instruction Header File
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4 | * @version V4.30
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5 | * @date 20. October 2015
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6 | ******************************************************************************/
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7 | /* Copyright (c) 2009 - 2015 ARM LIMITED
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8 |
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9 | All rights reserved.
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10 | Redistribution and use in source and binary forms, with or without
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11 | modification, are permitted provided that the following conditions are met:
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12 | - Redistributions of source code must retain the above copyright
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13 | notice, this list of conditions and the following disclaimer.
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14 | - Redistributions in binary form must reproduce the above copyright
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15 | notice, this list of conditions and the following disclaimer in the
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16 | documentation and/or other materials provided with the distribution.
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17 | - Neither the name of ARM nor the names of its contributors may be used
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18 | to endorse or promote products derived from this software without
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19 | specific prior written permission.
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20 | *
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21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31 | POSSIBILITY OF SUCH DAMAGE.
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32 | ---------------------------------------------------------------------------*/
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33 |
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34 |
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35 | #ifndef __CMSIS_GCC_H
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36 | #define __CMSIS_GCC_H
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37 |
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38 | /* ignore some GCC warnings */
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39 | #if defined ( __GNUC__ )
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40 | #pragma GCC diagnostic push
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41 | #pragma GCC diagnostic ignored "-Wsign-conversion"
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42 | #pragma GCC diagnostic ignored "-Wconversion"
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43 | #pragma GCC diagnostic ignored "-Wunused-parameter"
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44 | #endif
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45 |
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46 |
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47 | /* ########################### Core Function Access ########################### */
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48 | /** \ingroup CMSIS_Core_FunctionInterface
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49 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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50 | @{
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51 | */
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52 |
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53 | /**
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54 | \brief Enable IRQ Interrupts
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55 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
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56 | Can only be executed in Privileged modes.
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57 | */
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58 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
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59 | {
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60 | __ASM volatile ("cpsie i" : : : "memory");
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61 | }
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62 |
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63 |
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64 | /**
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65 | \brief Disable IRQ Interrupts
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66 | \details Disables IRQ interrupts by setting the I-bit in the CPSR.
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67 | Can only be executed in Privileged modes.
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68 | */
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69 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
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70 | {
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71 | __ASM volatile ("cpsid i" : : : "memory");
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72 | }
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73 |
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74 |
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75 | /**
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76 | \brief Get Control Register
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77 | \details Returns the content of the Control Register.
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78 | \return Control Register value
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79 | */
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80 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
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81 | {
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82 | uint32_t result;
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83 |
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84 | __ASM volatile ("MRS %0, control" : "=r" (result) );
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85 | return(result);
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86 | }
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87 |
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88 |
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89 | /**
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90 | \brief Set Control Register
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91 | \details Writes the given value to the Control Register.
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92 | \param [in] control Control Register value to set
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93 | */
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94 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
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95 | {
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96 | __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
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97 | }
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98 |
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99 |
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100 | /**
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101 | \brief Get IPSR Register
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102 | \details Returns the content of the IPSR Register.
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103 | \return IPSR Register value
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104 | */
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105 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
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106 | {
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107 | uint32_t result;
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108 |
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109 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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110 | return(result);
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111 | }
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112 |
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113 |
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114 | /**
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115 | \brief Get APSR Register
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116 | \details Returns the content of the APSR Register.
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117 | \return APSR Register value
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118 | */
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119 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
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120 | {
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121 | uint32_t result;
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122 |
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123 | __ASM volatile ("MRS %0, apsr" : "=r" (result) );
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124 | return(result);
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125 | }
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126 |
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127 |
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128 | /**
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129 | \brief Get xPSR Register
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130 | \details Returns the content of the xPSR Register.
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131 |
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132 | \return xPSR Register value
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133 | */
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134 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
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135 | {
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136 | uint32_t result;
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137 |
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138 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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139 | return(result);
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140 | }
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141 |
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142 |
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143 | /**
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144 | \brief Get Process Stack Pointer
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145 | \details Returns the current value of the Process Stack Pointer (PSP).
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146 | \return PSP Register value
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147 | */
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148 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
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149 | {
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150 | register uint32_t result;
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151 |
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152 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
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153 | return(result);
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154 | }
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155 |
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156 |
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157 | /**
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158 | \brief Set Process Stack Pointer
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159 | \details Assigns the given value to the Process Stack Pointer (PSP).
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160 | \param [in] topOfProcStack Process Stack Pointer value to set
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161 | */
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162 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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163 | {
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164 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
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165 | }
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166 |
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167 |
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168 | /**
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169 | \brief Get Main Stack Pointer
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170 | \details Returns the current value of the Main Stack Pointer (MSP).
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171 | \return MSP Register value
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172 | */
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173 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
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174 | {
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175 | register uint32_t result;
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176 |
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177 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
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178 | return(result);
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179 | }
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180 |
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181 |
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182 | /**
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183 | \brief Set Main Stack Pointer
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184 | \details Assigns the given value to the Main Stack Pointer (MSP).
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185 |
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186 | \param [in] topOfMainStack Main Stack Pointer value to set
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187 | */
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188 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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189 | {
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190 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
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191 | }
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192 |
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193 |
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194 | /**
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195 | \brief Get Priority Mask
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196 | \details Returns the current state of the priority mask bit from the Priority Mask Register.
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197 | \return Priority Mask value
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198 | */
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199 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
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200 | {
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201 | uint32_t result;
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202 |
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203 | __ASM volatile ("MRS %0, primask" : "=r" (result) );
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204 | return(result);
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205 | }
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206 |
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207 |
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208 | /**
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209 | \brief Set Priority Mask
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210 | \details Assigns the given value to the Priority Mask Register.
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211 | \param [in] priMask Priority Mask
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212 | */
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213 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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214 | {
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215 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
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216 | }
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217 |
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218 |
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219 | #if (__CORTEX_M >= 0x03U)
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220 |
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221 | /**
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222 | \brief Enable FIQ
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223 | \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
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224 | Can only be executed in Privileged modes.
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225 | */
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226 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
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227 | {
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228 | __ASM volatile ("cpsie f" : : : "memory");
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229 | }
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230 |
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231 |
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232 | /**
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233 | \brief Disable FIQ
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234 | \details Disables FIQ interrupts by setting the F-bit in the CPSR.
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235 | Can only be executed in Privileged modes.
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236 | */
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237 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
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238 | {
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239 | __ASM volatile ("cpsid f" : : : "memory");
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240 | }
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241 |
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242 |
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243 | /**
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244 | \brief Get Base Priority
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245 | \details Returns the current value of the Base Priority register.
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246 | \return Base Priority register value
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247 | */
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248 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
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249 | {
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250 | uint32_t result;
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251 |
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252 | __ASM volatile ("MRS %0, basepri" : "=r" (result) );
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253 | return(result);
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254 | }
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255 |
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256 |
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257 | /**
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258 | \brief Set Base Priority
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259 | \details Assigns the given value to the Base Priority register.
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260 | \param [in] basePri Base Priority value to set
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261 | */
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262 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
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263 | {
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264 | __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
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265 | }
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266 |
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267 |
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268 | /**
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269 | \brief Set Base Priority with condition
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270 | \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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271 | or the new value increases the BASEPRI priority level.
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272 | \param [in] basePri Base Priority value to set
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273 | */
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274 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
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275 | {
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276 | __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
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277 | }
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278 |
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279 |
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280 | /**
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281 | \brief Get Fault Mask
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282 | \details Returns the current value of the Fault Mask register.
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283 | \return Fault Mask register value
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284 | */
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285 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
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286 | {
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287 | uint32_t result;
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288 |
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289 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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290 | return(result);
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291 | }
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292 |
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293 |
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294 | /**
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295 | \brief Set Fault Mask
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296 | \details Assigns the given value to the Fault Mask register.
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297 | \param [in] faultMask Fault Mask value to set
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298 | */
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299 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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300 | {
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301 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
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302 | }
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303 |
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304 | #endif /* (__CORTEX_M >= 0x03U) */
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305 |
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306 |
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307 | #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
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308 |
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309 | /**
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310 | \brief Get FPSCR
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311 | \details Returns the current value of the Floating Point Status/Control register.
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312 | \return Floating Point Status/Control register value
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313 | */
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314 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
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315 | {
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316 | #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
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317 | uint32_t result;
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318 |
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319 | /* Empty asm statement works as a scheduling barrier */
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320 | __ASM volatile ("");
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321 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
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322 | __ASM volatile ("");
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323 | return(result);
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324 | #else
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325 | return(0);
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326 | #endif
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327 | }
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328 |
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329 |
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330 | /**
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331 | \brief Set FPSCR
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332 | \details Assigns the given value to the Floating Point Status/Control register.
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333 | \param [in] fpscr Floating Point Status/Control value to set
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334 | */
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335 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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336 | {
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337 | #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
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338 | /* Empty asm statement works as a scheduling barrier */
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339 | __ASM volatile ("");
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340 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
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341 | __ASM volatile ("");
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342 | #endif
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343 | }
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344 |
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345 | #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
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346 |
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347 |
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348 |
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349 | /*@} end of CMSIS_Core_RegAccFunctions */
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350 |
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351 |
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352 | /* ########################## Core Instruction Access ######################### */
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353 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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354 | \ingroup CMSIS
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355 | Access to dedicated instructions
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356 | @{
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357 | */
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358 |
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359 | /* Define macros for porting to both thumb1 and thumb2.
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360 | * For thumb1, use low register (r0-r7), specified by constraint "l"
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361 | * Otherwise, use general registers, specified by constraint "r" */
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362 | #if defined (__thumb__) && !defined (__thumb2__)
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363 | #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
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364 | #define __CMSIS_GCC_USE_REG(r) "l" (r)
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365 | #else
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366 | #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
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367 | #define __CMSIS_GCC_USE_REG(r) "r" (r)
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368 | #endif
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369 |
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370 | /**
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371 | \brief No Operation
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372 | \details No Operation does nothing. This instruction can be used for code alignment purposes.
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373 | */
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374 | __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
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375 | {
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376 | __ASM volatile ("nop");
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377 | }
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378 |
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379 |
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380 | /**
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381 | \brief Wait For Interrupt
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382 | \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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383 | */
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384 | __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
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385 | {
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386 | __ASM volatile ("wfi");
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387 | }
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388 |
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389 |
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390 | /**
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391 | \brief Wait For Event
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392 | \details Wait For Event is a hint instruction that permits the processor to enter
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393 | a low-power state until one of a number of events occurs.
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394 | */
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395 | __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
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396 | {
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397 | __ASM volatile ("wfe");
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398 | }
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399 |
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400 |
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401 | /**
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402 | \brief Send Event
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403 | \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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404 | */
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405 | __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
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406 | {
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407 | __ASM volatile ("sev");
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408 | }
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409 |
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410 |
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411 | /**
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412 | \brief Instruction Synchronization Barrier
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413 | \details Instruction Synchronization Barrier flushes the pipeline in the processor,
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414 | so that all instructions following the ISB are fetched from cache or memory,
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415 | after the instruction has been completed.
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416 | */
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417 | __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
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418 | {
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419 | __ASM volatile ("isb 0xF":::"memory");
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420 | }
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421 |
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422 |
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423 | /**
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424 | \brief Data Synchronization Barrier
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425 | \details Acts as a special kind of Data Memory Barrier.
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426 | It completes when all explicit memory accesses before this instruction complete.
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427 | */
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428 | __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
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429 | {
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430 | __ASM volatile ("dsb 0xF":::"memory");
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431 | }
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432 |
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433 |
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434 | /**
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435 | \brief Data Memory Barrier
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436 | \details Ensures the apparent order of the explicit memory operations before
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437 | and after the instruction, without ensuring their completion.
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438 | */
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439 | __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
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440 | {
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441 | __ASM volatile ("dmb 0xF":::"memory");
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442 | }
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443 |
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444 |
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445 | /**
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446 | \brief Reverse byte order (32 bit)
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447 | \details Reverses the byte order in integer value.
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448 | \param [in] value Value to reverse
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449 | \return Reversed value
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450 | */
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451 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
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452 | {
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453 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
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454 | return __builtin_bswap32(value);
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455 | #else
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456 | uint32_t result;
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457 |
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458 | __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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459 | return(result);
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460 | #endif
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461 | }
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462 |
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463 |
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464 | /**
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465 | \brief Reverse byte order (16 bit)
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466 | \details Reverses the byte order in two unsigned short values.
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467 | \param [in] value Value to reverse
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468 | \return Reversed value
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469 | */
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470 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
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471 | {
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472 | uint32_t result;
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473 |
|
---|
474 | __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
---|
475 | return(result);
|
---|
476 | }
|
---|
477 |
|
---|
478 |
|
---|
479 | /**
|
---|
480 | \brief Reverse byte order in signed short value
|
---|
481 | \details Reverses the byte order in a signed short value with sign extension to integer.
|
---|
482 | \param [in] value Value to reverse
|
---|
483 | \return Reversed value
|
---|
484 | */
|
---|
485 | __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
---|
486 | {
|
---|
487 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
488 | return (short)__builtin_bswap16(value);
|
---|
489 | #else
|
---|
490 | int32_t result;
|
---|
491 |
|
---|
492 | __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
---|
493 | return(result);
|
---|
494 | #endif
|
---|
495 | }
|
---|
496 |
|
---|
497 |
|
---|
498 | /**
|
---|
499 | \brief Rotate Right in unsigned value (32 bit)
|
---|
500 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
---|
501 | \param [in] value Value to rotate
|
---|
502 | \param [in] value Number of Bits to rotate
|
---|
503 | \return Rotated value
|
---|
504 | */
|
---|
505 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
---|
506 | {
|
---|
507 | return (op1 >> op2) | (op1 << (32U - op2));
|
---|
508 | }
|
---|
509 |
|
---|
510 |
|
---|
511 | /**
|
---|
512 | \brief Breakpoint
|
---|
513 | \details Causes the processor to enter Debug state.
|
---|
514 | Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
---|
515 | \param [in] value is ignored by the processor.
|
---|
516 | If required, a debugger can use it to store additional information about the breakpoint.
|
---|
517 | */
|
---|
518 | #define __BKPT(value) __ASM volatile ("bkpt "#value)
|
---|
519 |
|
---|
520 |
|
---|
521 | /**
|
---|
522 | \brief Reverse bit order of value
|
---|
523 | \details Reverses the bit order of the given value.
|
---|
524 | \param [in] value Value to reverse
|
---|
525 | \return Reversed value
|
---|
526 | */
|
---|
527 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
---|
528 | {
|
---|
529 | uint32_t result;
|
---|
530 |
|
---|
531 | #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
---|
532 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
---|
533 | #else
|
---|
534 | int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
---|
535 |
|
---|
536 | result = value; /* r will be reversed bits of v; first get LSB of v */
|
---|
537 | for (value >>= 1U; value; value >>= 1U)
|
---|
538 | {
|
---|
539 | result <<= 1U;
|
---|
540 | result |= value & 1U;
|
---|
541 | s--;
|
---|
542 | }
|
---|
543 | result <<= s; /* shift when v's highest bits are zero */
|
---|
544 | #endif
|
---|
545 | return(result);
|
---|
546 | }
|
---|
547 |
|
---|
548 |
|
---|
549 | /**
|
---|
550 | \brief Count leading zeros
|
---|
551 | \details Counts the number of leading zeros of a data value.
|
---|
552 | \param [in] value Value to count the leading zeros
|
---|
553 | \return number of leading zeros in value
|
---|
554 | */
|
---|
555 | #define __CLZ __builtin_clz
|
---|
556 |
|
---|
557 |
|
---|
558 | #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
---|
559 |
|
---|
560 | /**
|
---|
561 | \brief LDR Exclusive (8 bit)
|
---|
562 | \details Executes a exclusive LDR instruction for 8 bit value.
|
---|
563 | \param [in] ptr Pointer to data
|
---|
564 | \return value of type uint8_t at (*ptr)
|
---|
565 | */
|
---|
566 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
---|
567 | {
|
---|
568 | uint32_t result;
|
---|
569 |
|
---|
570 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
571 | __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
572 | #else
|
---|
573 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
574 | accepted by assembler. So has to use following less efficient pattern.
|
---|
575 | */
|
---|
576 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
577 | #endif
|
---|
578 | return ((uint8_t) result); /* Add explicit type cast here */
|
---|
579 | }
|
---|
580 |
|
---|
581 |
|
---|
582 | /**
|
---|
583 | \brief LDR Exclusive (16 bit)
|
---|
584 | \details Executes a exclusive LDR instruction for 16 bit values.
|
---|
585 | \param [in] ptr Pointer to data
|
---|
586 | \return value of type uint16_t at (*ptr)
|
---|
587 | */
|
---|
588 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
---|
589 | {
|
---|
590 | uint32_t result;
|
---|
591 |
|
---|
592 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
593 | __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
594 | #else
|
---|
595 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
596 | accepted by assembler. So has to use following less efficient pattern.
|
---|
597 | */
|
---|
598 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
599 | #endif
|
---|
600 | return ((uint16_t) result); /* Add explicit type cast here */
|
---|
601 | }
|
---|
602 |
|
---|
603 |
|
---|
604 | /**
|
---|
605 | \brief LDR Exclusive (32 bit)
|
---|
606 | \details Executes a exclusive LDR instruction for 32 bit values.
|
---|
607 | \param [in] ptr Pointer to data
|
---|
608 | \return value of type uint32_t at (*ptr)
|
---|
609 | */
|
---|
610 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
---|
611 | {
|
---|
612 | uint32_t result;
|
---|
613 |
|
---|
614 | __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
615 | return(result);
|
---|
616 | }
|
---|
617 |
|
---|
618 |
|
---|
619 | /**
|
---|
620 | \brief STR Exclusive (8 bit)
|
---|
621 | \details Executes a exclusive STR instruction for 8 bit values.
|
---|
622 | \param [in] value Value to store
|
---|
623 | \param [in] ptr Pointer to location
|
---|
624 | \return 0 Function succeeded
|
---|
625 | \return 1 Function failed
|
---|
626 | */
|
---|
627 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
---|
628 | {
|
---|
629 | uint32_t result;
|
---|
630 |
|
---|
631 | __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
632 | return(result);
|
---|
633 | }
|
---|
634 |
|
---|
635 |
|
---|
636 | /**
|
---|
637 | \brief STR Exclusive (16 bit)
|
---|
638 | \details Executes a exclusive STR instruction for 16 bit values.
|
---|
639 | \param [in] value Value to store
|
---|
640 | \param [in] ptr Pointer to location
|
---|
641 | \return 0 Function succeeded
|
---|
642 | \return 1 Function failed
|
---|
643 | */
|
---|
644 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
---|
645 | {
|
---|
646 | uint32_t result;
|
---|
647 |
|
---|
648 | __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
649 | return(result);
|
---|
650 | }
|
---|
651 |
|
---|
652 |
|
---|
653 | /**
|
---|
654 | \brief STR Exclusive (32 bit)
|
---|
655 | \details Executes a exclusive STR instruction for 32 bit values.
|
---|
656 | \param [in] value Value to store
|
---|
657 | \param [in] ptr Pointer to location
|
---|
658 | \return 0 Function succeeded
|
---|
659 | \return 1 Function failed
|
---|
660 | */
|
---|
661 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
---|
662 | {
|
---|
663 | uint32_t result;
|
---|
664 |
|
---|
665 | __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
---|
666 | return(result);
|
---|
667 | }
|
---|
668 |
|
---|
669 |
|
---|
670 | /**
|
---|
671 | \brief Remove the exclusive lock
|
---|
672 | \details Removes the exclusive lock which is created by LDREX.
|
---|
673 | */
|
---|
674 | __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
|
---|
675 | {
|
---|
676 | __ASM volatile ("clrex" ::: "memory");
|
---|
677 | }
|
---|
678 |
|
---|
679 |
|
---|
680 | /**
|
---|
681 | \brief Signed Saturate
|
---|
682 | \details Saturates a signed value.
|
---|
683 | \param [in] value Value to be saturated
|
---|
684 | \param [in] sat Bit position to saturate to (1..32)
|
---|
685 | \return Saturated value
|
---|
686 | */
|
---|
687 | #define __SSAT(ARG1,ARG2) \
|
---|
688 | ({ \
|
---|
689 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
690 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
691 | __RES; \
|
---|
692 | })
|
---|
693 |
|
---|
694 |
|
---|
695 | /**
|
---|
696 | \brief Unsigned Saturate
|
---|
697 | \details Saturates an unsigned value.
|
---|
698 | \param [in] value Value to be saturated
|
---|
699 | \param [in] sat Bit position to saturate to (0..31)
|
---|
700 | \return Saturated value
|
---|
701 | */
|
---|
702 | #define __USAT(ARG1,ARG2) \
|
---|
703 | ({ \
|
---|
704 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
705 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
706 | __RES; \
|
---|
707 | })
|
---|
708 |
|
---|
709 |
|
---|
710 | /**
|
---|
711 | \brief Rotate Right with Extend (32 bit)
|
---|
712 | \details Moves each bit of a bitstring right by one bit.
|
---|
713 | The carry input is shifted in at the left end of the bitstring.
|
---|
714 | \param [in] value Value to rotate
|
---|
715 | \return Rotated value
|
---|
716 | */
|
---|
717 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
---|
718 | {
|
---|
719 | uint32_t result;
|
---|
720 |
|
---|
721 | __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
---|
722 | return(result);
|
---|
723 | }
|
---|
724 |
|
---|
725 |
|
---|
726 | /**
|
---|
727 | \brief LDRT Unprivileged (8 bit)
|
---|
728 | \details Executes a Unprivileged LDRT instruction for 8 bit value.
|
---|
729 | \param [in] ptr Pointer to data
|
---|
730 | \return value of type uint8_t at (*ptr)
|
---|
731 | */
|
---|
732 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
---|
733 | {
|
---|
734 | uint32_t result;
|
---|
735 |
|
---|
736 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
737 | __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
738 | #else
|
---|
739 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
740 | accepted by assembler. So has to use following less efficient pattern.
|
---|
741 | */
|
---|
742 | __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
743 | #endif
|
---|
744 | return ((uint8_t) result); /* Add explicit type cast here */
|
---|
745 | }
|
---|
746 |
|
---|
747 |
|
---|
748 | /**
|
---|
749 | \brief LDRT Unprivileged (16 bit)
|
---|
750 | \details Executes a Unprivileged LDRT instruction for 16 bit values.
|
---|
751 | \param [in] ptr Pointer to data
|
---|
752 | \return value of type uint16_t at (*ptr)
|
---|
753 | */
|
---|
754 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
---|
755 | {
|
---|
756 | uint32_t result;
|
---|
757 |
|
---|
758 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
759 | __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
760 | #else
|
---|
761 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
762 | accepted by assembler. So has to use following less efficient pattern.
|
---|
763 | */
|
---|
764 | __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
765 | #endif
|
---|
766 | return ((uint16_t) result); /* Add explicit type cast here */
|
---|
767 | }
|
---|
768 |
|
---|
769 |
|
---|
770 | /**
|
---|
771 | \brief LDRT Unprivileged (32 bit)
|
---|
772 | \details Executes a Unprivileged LDRT instruction for 32 bit values.
|
---|
773 | \param [in] ptr Pointer to data
|
---|
774 | \return value of type uint32_t at (*ptr)
|
---|
775 | */
|
---|
776 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
---|
777 | {
|
---|
778 | uint32_t result;
|
---|
779 |
|
---|
780 | __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
781 | return(result);
|
---|
782 | }
|
---|
783 |
|
---|
784 |
|
---|
785 | /**
|
---|
786 | \brief STRT Unprivileged (8 bit)
|
---|
787 | \details Executes a Unprivileged STRT instruction for 8 bit values.
|
---|
788 | \param [in] value Value to store
|
---|
789 | \param [in] ptr Pointer to location
|
---|
790 | */
|
---|
791 | __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
---|
792 | {
|
---|
793 | __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
794 | }
|
---|
795 |
|
---|
796 |
|
---|
797 | /**
|
---|
798 | \brief STRT Unprivileged (16 bit)
|
---|
799 | \details Executes a Unprivileged STRT instruction for 16 bit values.
|
---|
800 | \param [in] value Value to store
|
---|
801 | \param [in] ptr Pointer to location
|
---|
802 | */
|
---|
803 | __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
---|
804 | {
|
---|
805 | __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
806 | }
|
---|
807 |
|
---|
808 |
|
---|
809 | /**
|
---|
810 | \brief STRT Unprivileged (32 bit)
|
---|
811 | \details Executes a Unprivileged STRT instruction for 32 bit values.
|
---|
812 | \param [in] value Value to store
|
---|
813 | \param [in] ptr Pointer to location
|
---|
814 | */
|
---|
815 | __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
---|
816 | {
|
---|
817 | __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
---|
818 | }
|
---|
819 |
|
---|
820 | #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
---|
821 |
|
---|
822 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
---|
823 |
|
---|
824 |
|
---|
825 | /* ################### Compiler specific Intrinsics ########################### */
|
---|
826 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
---|
827 | \ingroup CMSIS
|
---|
828 | Access to dedicated SIMD instructions
|
---|
829 | @{
|
---|
830 | */
|
---|
831 |
|
---|
832 | #if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
---|
833 |
|
---|
834 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
---|
835 | {
|
---|
836 | uint32_t result;
|
---|
837 |
|
---|
838 | __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
839 | return(result);
|
---|
840 | }
|
---|
841 |
|
---|
842 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
---|
843 | {
|
---|
844 | uint32_t result;
|
---|
845 |
|
---|
846 | __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
847 | return(result);
|
---|
848 | }
|
---|
849 |
|
---|
850 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
---|
851 | {
|
---|
852 | uint32_t result;
|
---|
853 |
|
---|
854 | __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
855 | return(result);
|
---|
856 | }
|
---|
857 |
|
---|
858 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
---|
859 | {
|
---|
860 | uint32_t result;
|
---|
861 |
|
---|
862 | __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
863 | return(result);
|
---|
864 | }
|
---|
865 |
|
---|
866 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
---|
867 | {
|
---|
868 | uint32_t result;
|
---|
869 |
|
---|
870 | __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
871 | return(result);
|
---|
872 | }
|
---|
873 |
|
---|
874 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
---|
875 | {
|
---|
876 | uint32_t result;
|
---|
877 |
|
---|
878 | __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
879 | return(result);
|
---|
880 | }
|
---|
881 |
|
---|
882 |
|
---|
883 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
---|
884 | {
|
---|
885 | uint32_t result;
|
---|
886 |
|
---|
887 | __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
888 | return(result);
|
---|
889 | }
|
---|
890 |
|
---|
891 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
---|
892 | {
|
---|
893 | uint32_t result;
|
---|
894 |
|
---|
895 | __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
896 | return(result);
|
---|
897 | }
|
---|
898 |
|
---|
899 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
---|
900 | {
|
---|
901 | uint32_t result;
|
---|
902 |
|
---|
903 | __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
904 | return(result);
|
---|
905 | }
|
---|
906 |
|
---|
907 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
---|
908 | {
|
---|
909 | uint32_t result;
|
---|
910 |
|
---|
911 | __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
912 | return(result);
|
---|
913 | }
|
---|
914 |
|
---|
915 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
---|
916 | {
|
---|
917 | uint32_t result;
|
---|
918 |
|
---|
919 | __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
920 | return(result);
|
---|
921 | }
|
---|
922 |
|
---|
923 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
---|
924 | {
|
---|
925 | uint32_t result;
|
---|
926 |
|
---|
927 | __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
928 | return(result);
|
---|
929 | }
|
---|
930 |
|
---|
931 |
|
---|
932 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
---|
933 | {
|
---|
934 | uint32_t result;
|
---|
935 |
|
---|
936 | __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
937 | return(result);
|
---|
938 | }
|
---|
939 |
|
---|
940 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
---|
941 | {
|
---|
942 | uint32_t result;
|
---|
943 |
|
---|
944 | __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
945 | return(result);
|
---|
946 | }
|
---|
947 |
|
---|
948 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
---|
949 | {
|
---|
950 | uint32_t result;
|
---|
951 |
|
---|
952 | __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
953 | return(result);
|
---|
954 | }
|
---|
955 |
|
---|
956 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
---|
957 | {
|
---|
958 | uint32_t result;
|
---|
959 |
|
---|
960 | __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
961 | return(result);
|
---|
962 | }
|
---|
963 |
|
---|
964 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
---|
965 | {
|
---|
966 | uint32_t result;
|
---|
967 |
|
---|
968 | __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
969 | return(result);
|
---|
970 | }
|
---|
971 |
|
---|
972 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
---|
973 | {
|
---|
974 | uint32_t result;
|
---|
975 |
|
---|
976 | __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
977 | return(result);
|
---|
978 | }
|
---|
979 |
|
---|
980 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
---|
981 | {
|
---|
982 | uint32_t result;
|
---|
983 |
|
---|
984 | __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
985 | return(result);
|
---|
986 | }
|
---|
987 |
|
---|
988 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
---|
989 | {
|
---|
990 | uint32_t result;
|
---|
991 |
|
---|
992 | __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
993 | return(result);
|
---|
994 | }
|
---|
995 |
|
---|
996 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
---|
997 | {
|
---|
998 | uint32_t result;
|
---|
999 |
|
---|
1000 | __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1001 | return(result);
|
---|
1002 | }
|
---|
1003 |
|
---|
1004 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
---|
1005 | {
|
---|
1006 | uint32_t result;
|
---|
1007 |
|
---|
1008 | __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1009 | return(result);
|
---|
1010 | }
|
---|
1011 |
|
---|
1012 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
---|
1013 | {
|
---|
1014 | uint32_t result;
|
---|
1015 |
|
---|
1016 | __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1017 | return(result);
|
---|
1018 | }
|
---|
1019 |
|
---|
1020 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
---|
1021 | {
|
---|
1022 | uint32_t result;
|
---|
1023 |
|
---|
1024 | __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1025 | return(result);
|
---|
1026 | }
|
---|
1027 |
|
---|
1028 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
---|
1029 | {
|
---|
1030 | uint32_t result;
|
---|
1031 |
|
---|
1032 | __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1033 | return(result);
|
---|
1034 | }
|
---|
1035 |
|
---|
1036 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
---|
1037 | {
|
---|
1038 | uint32_t result;
|
---|
1039 |
|
---|
1040 | __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1041 | return(result);
|
---|
1042 | }
|
---|
1043 |
|
---|
1044 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
---|
1045 | {
|
---|
1046 | uint32_t result;
|
---|
1047 |
|
---|
1048 | __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1049 | return(result);
|
---|
1050 | }
|
---|
1051 |
|
---|
1052 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
---|
1053 | {
|
---|
1054 | uint32_t result;
|
---|
1055 |
|
---|
1056 | __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1057 | return(result);
|
---|
1058 | }
|
---|
1059 |
|
---|
1060 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
---|
1061 | {
|
---|
1062 | uint32_t result;
|
---|
1063 |
|
---|
1064 | __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1065 | return(result);
|
---|
1066 | }
|
---|
1067 |
|
---|
1068 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
---|
1069 | {
|
---|
1070 | uint32_t result;
|
---|
1071 |
|
---|
1072 | __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1073 | return(result);
|
---|
1074 | }
|
---|
1075 |
|
---|
1076 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
---|
1077 | {
|
---|
1078 | uint32_t result;
|
---|
1079 |
|
---|
1080 | __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1081 | return(result);
|
---|
1082 | }
|
---|
1083 |
|
---|
1084 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
---|
1085 | {
|
---|
1086 | uint32_t result;
|
---|
1087 |
|
---|
1088 | __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1089 | return(result);
|
---|
1090 | }
|
---|
1091 |
|
---|
1092 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
---|
1093 | {
|
---|
1094 | uint32_t result;
|
---|
1095 |
|
---|
1096 | __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1097 | return(result);
|
---|
1098 | }
|
---|
1099 |
|
---|
1100 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
---|
1101 | {
|
---|
1102 | uint32_t result;
|
---|
1103 |
|
---|
1104 | __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1105 | return(result);
|
---|
1106 | }
|
---|
1107 |
|
---|
1108 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
---|
1109 | {
|
---|
1110 | uint32_t result;
|
---|
1111 |
|
---|
1112 | __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1113 | return(result);
|
---|
1114 | }
|
---|
1115 |
|
---|
1116 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
---|
1117 | {
|
---|
1118 | uint32_t result;
|
---|
1119 |
|
---|
1120 | __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1121 | return(result);
|
---|
1122 | }
|
---|
1123 |
|
---|
1124 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
---|
1125 | {
|
---|
1126 | uint32_t result;
|
---|
1127 |
|
---|
1128 | __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1129 | return(result);
|
---|
1130 | }
|
---|
1131 |
|
---|
1132 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
1133 | {
|
---|
1134 | uint32_t result;
|
---|
1135 |
|
---|
1136 | __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
1137 | return(result);
|
---|
1138 | }
|
---|
1139 |
|
---|
1140 | #define __SSAT16(ARG1,ARG2) \
|
---|
1141 | ({ \
|
---|
1142 | int32_t __RES, __ARG1 = (ARG1); \
|
---|
1143 | __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
1144 | __RES; \
|
---|
1145 | })
|
---|
1146 |
|
---|
1147 | #define __USAT16(ARG1,ARG2) \
|
---|
1148 | ({ \
|
---|
1149 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
1150 | __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
1151 | __RES; \
|
---|
1152 | })
|
---|
1153 |
|
---|
1154 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
---|
1155 | {
|
---|
1156 | uint32_t result;
|
---|
1157 |
|
---|
1158 | __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
---|
1159 | return(result);
|
---|
1160 | }
|
---|
1161 |
|
---|
1162 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
---|
1163 | {
|
---|
1164 | uint32_t result;
|
---|
1165 |
|
---|
1166 | __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1167 | return(result);
|
---|
1168 | }
|
---|
1169 |
|
---|
1170 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
---|
1171 | {
|
---|
1172 | uint32_t result;
|
---|
1173 |
|
---|
1174 | __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
---|
1175 | return(result);
|
---|
1176 | }
|
---|
1177 |
|
---|
1178 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
---|
1179 | {
|
---|
1180 | uint32_t result;
|
---|
1181 |
|
---|
1182 | __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1183 | return(result);
|
---|
1184 | }
|
---|
1185 |
|
---|
1186 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
---|
1187 | {
|
---|
1188 | uint32_t result;
|
---|
1189 |
|
---|
1190 | __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1191 | return(result);
|
---|
1192 | }
|
---|
1193 |
|
---|
1194 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
---|
1195 | {
|
---|
1196 | uint32_t result;
|
---|
1197 |
|
---|
1198 | __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1199 | return(result);
|
---|
1200 | }
|
---|
1201 |
|
---|
1202 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
1203 | {
|
---|
1204 | uint32_t result;
|
---|
1205 |
|
---|
1206 | __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
1207 | return(result);
|
---|
1208 | }
|
---|
1209 |
|
---|
1210 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
1211 | {
|
---|
1212 | uint32_t result;
|
---|
1213 |
|
---|
1214 | __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
1215 | return(result);
|
---|
1216 | }
|
---|
1217 |
|
---|
1218 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
1219 | {
|
---|
1220 | union llreg_u{
|
---|
1221 | uint32_t w32[2];
|
---|
1222 | uint64_t w64;
|
---|
1223 | } llr;
|
---|
1224 | llr.w64 = acc;
|
---|
1225 |
|
---|
1226 | #ifndef __ARMEB__ /* Little endian */
|
---|
1227 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
1228 | #else /* Big endian */
|
---|
1229 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
1230 | #endif
|
---|
1231 |
|
---|
1232 | return(llr.w64);
|
---|
1233 | }
|
---|
1234 |
|
---|
1235 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
1236 | {
|
---|
1237 | union llreg_u{
|
---|
1238 | uint32_t w32[2];
|
---|
1239 | uint64_t w64;
|
---|
1240 | } llr;
|
---|
1241 | llr.w64 = acc;
|
---|
1242 |
|
---|
1243 | #ifndef __ARMEB__ /* Little endian */
|
---|
1244 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
1245 | #else /* Big endian */
|
---|
1246 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
1247 | #endif
|
---|
1248 |
|
---|
1249 | return(llr.w64);
|
---|
1250 | }
|
---|
1251 |
|
---|
1252 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
---|
1253 | {
|
---|
1254 | uint32_t result;
|
---|
1255 |
|
---|
1256 | __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1257 | return(result);
|
---|
1258 | }
|
---|
1259 |
|
---|
1260 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
---|
1261 | {
|
---|
1262 | uint32_t result;
|
---|
1263 |
|
---|
1264 | __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1265 | return(result);
|
---|
1266 | }
|
---|
1267 |
|
---|
1268 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
1269 | {
|
---|
1270 | uint32_t result;
|
---|
1271 |
|
---|
1272 | __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
1273 | return(result);
|
---|
1274 | }
|
---|
1275 |
|
---|
1276 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
1277 | {
|
---|
1278 | uint32_t result;
|
---|
1279 |
|
---|
1280 | __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
1281 | return(result);
|
---|
1282 | }
|
---|
1283 |
|
---|
1284 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
1285 | {
|
---|
1286 | union llreg_u{
|
---|
1287 | uint32_t w32[2];
|
---|
1288 | uint64_t w64;
|
---|
1289 | } llr;
|
---|
1290 | llr.w64 = acc;
|
---|
1291 |
|
---|
1292 | #ifndef __ARMEB__ /* Little endian */
|
---|
1293 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
1294 | #else /* Big endian */
|
---|
1295 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
1296 | #endif
|
---|
1297 |
|
---|
1298 | return(llr.w64);
|
---|
1299 | }
|
---|
1300 |
|
---|
1301 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
---|
1302 | {
|
---|
1303 | union llreg_u{
|
---|
1304 | uint32_t w32[2];
|
---|
1305 | uint64_t w64;
|
---|
1306 | } llr;
|
---|
1307 | llr.w64 = acc;
|
---|
1308 |
|
---|
1309 | #ifndef __ARMEB__ /* Little endian */
|
---|
1310 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
---|
1311 | #else /* Big endian */
|
---|
1312 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
---|
1313 | #endif
|
---|
1314 |
|
---|
1315 | return(llr.w64);
|
---|
1316 | }
|
---|
1317 |
|
---|
1318 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
---|
1319 | {
|
---|
1320 | uint32_t result;
|
---|
1321 |
|
---|
1322 | __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1323 | return(result);
|
---|
1324 | }
|
---|
1325 |
|
---|
1326 | __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
|
---|
1327 | {
|
---|
1328 | int32_t result;
|
---|
1329 |
|
---|
1330 | __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1331 | return(result);
|
---|
1332 | }
|
---|
1333 |
|
---|
1334 | __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
|
---|
1335 | {
|
---|
1336 | int32_t result;
|
---|
1337 |
|
---|
1338 | __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
1339 | return(result);
|
---|
1340 | }
|
---|
1341 |
|
---|
1342 | #define __PKHBT(ARG1,ARG2,ARG3) \
|
---|
1343 | ({ \
|
---|
1344 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
---|
1345 | __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
---|
1346 | __RES; \
|
---|
1347 | })
|
---|
1348 |
|
---|
1349 | #define __PKHTB(ARG1,ARG2,ARG3) \
|
---|
1350 | ({ \
|
---|
1351 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
---|
1352 | if (ARG3 == 0) \
|
---|
1353 | __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
---|
1354 | else \
|
---|
1355 | __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
---|
1356 | __RES; \
|
---|
1357 | })
|
---|
1358 |
|
---|
1359 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
---|
1360 | {
|
---|
1361 | int32_t result;
|
---|
1362 |
|
---|
1363 | __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
---|
1364 | return(result);
|
---|
1365 | }
|
---|
1366 |
|
---|
1367 | #endif /* (__CORTEX_M >= 0x04) */
|
---|
1368 | /*@} end of group CMSIS_SIMD_intrinsics */
|
---|
1369 |
|
---|
1370 |
|
---|
1371 | #if defined ( __GNUC__ )
|
---|
1372 | #pragma GCC diagnostic pop
|
---|
1373 | #endif
|
---|
1374 |
|
---|
1375 | #endif /* __CMSIS_GCC_H */
|
---|