source: rtems/bsps/arm/include/bsp/lpc-timer.h @ ba619b7f

Last change on this file since ba619b7f was ba619b7f, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:20

bsps/arm/: Scripted embedded brains header file clean up

Updates #4625.
  • Property mode set to 100644
File size: 2.8 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc_timer
5 *
6 * @brief Timer API.
7 */
8
9/*
10 * Copyright (c) 2009 embedded brains GmbH.  All rights reserved.
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.org/license/LICENSE.
15 */
16
17#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H
18#define LIBBSP_ARM_SHARED_LPC_TIMER_H
19
20#include <stdint.h>
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/**
27 * @defgroup lpc_timer Timer Support
28 *
29 * @ingroup RTEMSBSPsARMLPC24XX
30 * @ingroup RTEMSBSPsARMLPC32XX
31 *
32 * @brief Timer support.
33 *
34 * @{
35 */
36
37/**
38 * @name Interrupt Register Defines
39 *
40 * @{
41 */
42
43#define LPC_TIMER_IR_MR0 0x1U
44#define LPC_TIMER_IR_MR1 0x2U
45#define LPC_TIMER_IR_MR2 0x4U
46#define LPC_TIMER_IR_MR3 0x8U
47#define LPC_TIMER_IR_CR0 0x10U
48#define LPC_TIMER_IR_CR1 0x20U
49#define LPC_TIMER_IR_CR2 0x40U
50#define LPC_TIMER_IR_CR3 0x80U
51#define LPC_TIMER_IR_ALL 0xffU
52
53/** @} */
54
55/**
56 * @name Timer Control Register Defines
57 *
58 * @{
59 */
60
61#define LPC_TIMER_TCR_EN 0x1U
62#define LPC_TIMER_TCR_RST 0x2U
63
64/** @} */
65
66/**
67 * @name Match Control Register Defines
68 *
69 * @{
70 */
71
72#define LPC_TIMER_MCR_MR0_INTR 0x1U
73#define LPC_TIMER_MCR_MR0_RST 0x2U
74#define LPC_TIMER_MCR_MR0_STOP 0x4U
75#define LPC_TIMER_MCR_MR1_INTR 0x8U
76#define LPC_TIMER_MCR_MR1_RST 0x10U
77#define LPC_TIMER_MCR_MR1_STOP 0x20U
78#define LPC_TIMER_MCR_MR2_INTR 0x40U
79#define LPC_TIMER_MCR_MR2_RST 0x80U
80#define LPC_TIMER_MCR_MR2_STOP 0x100U
81#define LPC_TIMER_MCR_MR3_INTR 0x200U
82#define LPC_TIMER_MCR_MR3_RST 0x400U
83#define LPC_TIMER_MCR_MR3_STOP 0x800U
84
85/** @} */
86
87/**
88 * @name Capture Control Register Defines
89 *
90 * @{
91 */
92
93#define LPC_TIMER_CCR_CAP0_RE 0x1U
94#define LPC_TIMER_CCR_CAP0_FE 0x2U
95#define LPC_TIMER_CCR_CAP0_INTR 0x4U
96#define LPC_TIMER_CCR_CAP1_RE 0x8U
97#define LPC_TIMER_CCR_CAP1_FE 0x10U
98#define LPC_TIMER_CCR_CAP1_INTR 0x20U
99#define LPC_TIMER_CCR_CAP2_RE 0x40U
100#define LPC_TIMER_CCR_CAP2_FE 0x80U
101#define LPC_TIMER_CCR_CAP2_INTR 0x100U
102#define LPC_TIMER_CCR_CAP3_RE 0x200U
103#define LPC_TIMER_CCR_CAP3_FE 0x400U
104#define LPC_TIMER_CCR_CAP3_INTR 0x800U
105
106/** @} */
107
108/**
109 * @name External Match Register Defines
110 *
111 * @{
112 */
113
114#define LPC_TIMER_EMR_EM0_RE 0x1U
115#define LPC_TIMER_EMR_EM1_FE 0x2U
116#define LPC_TIMER_EMR_EM2_INTR 0x4U
117#define LPC_TIMER_EMR_EM3_RE 0x8U
118#define LPC_TIMER_EMR_EMC0_FE 0x10U
119#define LPC_TIMER_EMR_EMC1_INTR 0x20U
120#define LPC_TIMER_EMR_EMC2_RE 0x40U
121#define LPC_TIMER_EMR_EMC3_FE 0x80U
122
123/** @} */
124
125/**
126 * @brief Timer control block.
127 */
128typedef struct {
129  uint32_t ir;
130  uint32_t tcr;
131  uint32_t tc;
132  uint32_t pr;
133  uint32_t pc;
134  uint32_t mcr;
135  uint32_t mr0;
136  uint32_t mr1;
137  uint32_t mr2;
138  uint32_t mr3;
139  uint32_t ccr;
140  uint32_t cr0;
141  uint32_t cr1;
142  uint32_t cr2;
143  uint32_t cr3;
144  uint32_t emr;
145  uint32_t ctcr;
146} lpc_timer;
147
148/** @} */
149
150#ifdef __cplusplus
151}
152#endif /* __cplusplus */
153
154#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */
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