source: rtems/bsps/arm/include/bsp/arm-pl111-regs.h @ ba619b7f

Last change on this file since ba619b7f was ba619b7f, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:20

bsps/arm/: Scripted embedded brains header file clean up

Updates #4625.
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File size: 7.8 KB
Line 
1/**
2 *  @file
3 *
4 *  @ingroup RTEMSBSPsARMShared
5 *
6 *  @brief ARM PL111 Register definitions
7 */
8
9/*
10 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.org/license/LICENSE.
15 */
16
17#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
18#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
19
20#include <bsp/utility.h>
21
22typedef struct {
23        uint32_t timing0;
24#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7)
25#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
26#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7)
27#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15)
28#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
29#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
30#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23)
31#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
32#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
33#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31)
34#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
35#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
36        uint32_t timing1;
37#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9)
38#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
39#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
40#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15)
41#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
42#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15)
43#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23)
44#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
45#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
46#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31)
47#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
48#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
49        uint32_t timing2;
50#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4)
51#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
52#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
53#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5)
54#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10)
55#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
56#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
57#define PL111_LCD_TIMING2_IVS BSP_BIT32(11)
58#define PL111_LCD_TIMING2_IHS BSP_BIT32(12)
59#define PL111_LCD_TIMING2_IPC BSP_BIT32(13)
60#define PL111_LCD_TIMING2_IOE BSP_BIT32(14)
61#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25)
62#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
63#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
64#define PL111_LCD_TIMING2_BCD BSP_BIT32(26)
65#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31)
66#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
67#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31)
68        uint32_t timing3;
69#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6)
70#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6)
71#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
72#define PL111_LCD_TIMING3_LEE BSP_BIT32(16)
73        uint32_t upbase;
74        uint32_t lpbase;
75        uint32_t control;
76#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0)
77#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3)
78#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
79#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3)
80#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U
81#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U
82#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U
83#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U
84#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U
85#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U
86#define PL111_LCD_CONTROL_LCD_BPP_16_5_6_5 0x06U
87#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U
88#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4)
89#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5)
90#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6)
91#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7)
92#define PL111_LCD_CONTROL_BGR BSP_BIT32(8)
93#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9)
94#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10)
95#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11)
96#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13)
97#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
98#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
99#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16)
100        uint32_t imsc;
101        uint32_t ris;
102        uint32_t mis;
103        uint32_t icr;
104#define PL111_LCD_I_FUF BSP_BIT32(1)
105#define PL111_LCD_I_LNBU BSP_BIT32(2)
106#define PL111_LCD_I_VCOMP BSP_BIT32(3)
107#define PL111_LCD_I_MBERROR BSP_BIT32(4)
108        uint32_t upcurr;
109        uint32_t lpcurr;
110        uint32_t reserved_34[115];
111        uint16_t pal[256];
112#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
113#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4)
114#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4)
115#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
116#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9)
117#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9)
118#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
119#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14)
120#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14)
121#define PL111_LCD_PAL_I BSP_BIT16(15)
122} pl111_lcd;
123
124typedef struct {
125        uint8_t image[1024];
126        uint32_t ctrl;
127#define PL111_CRSR_CTRL_ON BSP_BIT32(0)
128#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5)
129#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5)
130#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
131        uint32_t config;
132#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0)
133#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1)
134        uint32_t palette0;
135        uint32_t palette1;
136#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7)
137#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7)
138#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
139#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15)
140#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15)
141#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
142#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23)
143#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23)
144#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
145        uint32_t xy;
146#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9)
147#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9)
148#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
149#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11)
150#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11)
151#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11)
152#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25)
153#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25)
154#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
155#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27)
156#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27)
157#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27)
158        uint32_t clip;
159#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5)
160#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5)
161#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
162#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13)
163#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13)
164#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
165        uint32_t imsc;
166        uint32_t icr;
167        uint32_t ris;
168        uint32_t mis;
169#define PL111_CRSR_I_CRSR BSP_BIT32(0)
170} pl111_crsr;
171
172typedef struct {
173        pl111_lcd lcd;
174        uint32_t reserved_400[256];
175        pl111_crsr crsr;
176} pl111;
177
178#endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */
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