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1 | /* |
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2 | * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <rtems/score/armv7m.h> |
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16 | |
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17 | #include <bsp.h> |
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18 | #include <imxrt/mpu-config.h> |
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19 | |
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20 | #include <chip.h> |
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21 | #include <fsl_pin_mux.h> |
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22 | #include <fsl_clock_config.h> |
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23 | |
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24 | BSP_START_TEXT_SECTION void bsp_start_hook_0(void) |
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25 | { |
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26 | /* FIXME: Initializing SDRAM is currently done by DCD. It would be more user |
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27 | * friendly if that would be done here with a readable structure. */ |
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28 | if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) { |
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29 | SCB_EnableICache(); |
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30 | } |
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31 | |
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32 | if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) { |
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33 | SCB_EnableDCache(); |
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34 | } |
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35 | |
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36 | _ARMV7M_MPU_Setup(imxrt_config_mpu_region, imxrt_config_mpu_region_count); |
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37 | } |
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38 | |
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39 | BSP_START_TEXT_SECTION void bsp_start_hook_1(void) |
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40 | { |
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41 | bsp_start_copy_sections_compact(); |
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42 | SCB_CleanDCache(); |
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43 | SCB_InvalidateICache(); |
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44 | bsp_start_clear_bss(); |
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45 | |
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46 | BOARD_BootClockRUN(); |
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47 | BOARD_InitDEBUG_UARTPins(); |
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48 | |
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49 | /* Reduce frequency for I2C */ |
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50 | CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); |
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51 | } |
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