source: rtems/bsps/arm/imxrt/start/bspstarthooks.c @ 7141afbb

Last change on this file since 7141afbb was 7141afbb, checked in by Christian Mauderer <christian.mauderer@…>, on 10/09/20 at 13:55:35

bsp/imxrt: Add new BSP

Update #4180

  • Property mode set to 100644
File size: 1.2 KB
Line 
1/*
2 * Copyright (c) 2013, 2018 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <rtems/score/armv7m.h>
16
17#include <bsp.h>
18#include <imxrt/mpu-config.h>
19
20#include <chip.h>
21#include <fsl_pin_mux.h>
22#include <fsl_clock_config.h>
23
24BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
25{
26  /* FIXME: Initializing SDRAM is currently done by DCD. It would be more user
27   * friendly if that would be done here with a readable structure. */
28  if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
29    SCB_EnableICache();
30  }
31
32  if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
33    SCB_EnableDCache();
34  }
35
36  _ARMV7M_MPU_Setup(imxrt_config_mpu_region, imxrt_config_mpu_region_count);
37}
38
39BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
40{
41  bsp_start_copy_sections_compact();
42  SCB_CleanDCache();
43  SCB_InvalidateICache();
44  bsp_start_clear_bss();
45
46  BOARD_BootClockRUN();
47  BOARD_InitDEBUG_UARTPins();
48
49  /* Reduce frequency for I2C */
50  CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
51}
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