1 | /* |
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2 | * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION |
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16 | |
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17 | #include <bsp.h> |
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18 | #include <bsp/bootcard.h> |
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19 | #include <bsp/fdt.h> |
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20 | #include <bsp/linker-symbols.h> |
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21 | #include <bsp/start.h> |
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22 | #include <bsp/arm-cp15-start.h> |
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23 | #include <bsp/arm-a9mpcore-start.h> |
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24 | |
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25 | #include <rtems/sysinit.h> |
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26 | |
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27 | #include <libfdt.h> |
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28 | |
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29 | BSP_START_DATA_SECTION static arm_cp15_start_section_config |
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30 | imx_mmu_config_table[] = { |
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31 | ARMV7_CP15_START_DEFAULT_SECTIONS, |
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32 | { |
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33 | .begin = 0x00a00000U, |
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34 | .end = 0x70000000U, |
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35 | .flags = ARMV7_MMU_DEVICE |
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36 | } |
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37 | }; |
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38 | |
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39 | BSP_START_DATA_SECTION static char memory_path[] = "/memory"; |
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40 | |
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41 | BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void) |
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42 | { |
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43 | const void *fdt; |
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44 | int node; |
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45 | uint32_t ctrl; |
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46 | |
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47 | fdt = bsp_fdt_get(); |
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48 | node = fdt_path_offset_namelen( |
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49 | fdt, |
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50 | memory_path, |
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51 | (int) sizeof(memory_path) - 1 |
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52 | ); |
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53 | |
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54 | if (node >= 0) { |
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55 | int len; |
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56 | const void *val; |
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57 | |
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58 | val = fdt_getprop(fdt, node, "reg", &len); |
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59 | if (len == 8) { |
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60 | uint32_t begin; |
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61 | uint32_t size; |
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62 | |
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63 | begin = fdt32_to_cpu(((fdt32_t *) val)[0]); |
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64 | size = fdt32_to_cpu(((fdt32_t *) val)[1]); |
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65 | |
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66 | /* The heap code does not like an end address of zero */ |
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67 | if (begin + size == 0) { |
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68 | size -= 4; |
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69 | } |
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70 | |
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71 | imx_mmu_config_table[ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX].end = |
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72 | begin + size; |
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73 | } |
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74 | } |
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75 | |
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76 | ctrl = arm_cp15_start_setup_mmu_and_cache( |
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77 | ARM_CP15_CTRL_A, |
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78 | ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z |
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79 | ); |
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80 | |
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81 | arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( |
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82 | ctrl, |
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83 | (uint32_t *) bsp_translation_table_base, |
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84 | ARM_MMU_DEFAULT_CLIENT_DOMAIN, |
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85 | &imx_mmu_config_table[0], |
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86 | RTEMS_ARRAY_SIZE(imx_mmu_config_table) |
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87 | ); |
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88 | } |
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89 | |
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90 | BSP_START_TEXT_SECTION void bsp_start_hook_0(void) |
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91 | { |
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92 | #ifdef RTEMS_SMP |
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93 | uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); |
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94 | |
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95 | arm_a9mpcore_start_enable_smp_in_auxiliary_control(); |
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96 | |
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97 | if (cpu_id != 0) { |
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98 | arm_a9mpcore_start_on_secondary_processor(); |
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99 | } |
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100 | #endif |
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101 | } |
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102 | |
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103 | BSP_START_TEXT_SECTION void bsp_start_hook_1(void) |
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104 | { |
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105 | bsp_start_copy_sections(); |
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106 | setup_mmu_and_cache(); |
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107 | bsp_start_clear_bss(); |
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108 | } |
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109 | |
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110 | static Memory_Area _Memory_Areas[1]; |
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111 | |
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112 | static void bsp_memory_initialize(void) |
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113 | { |
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114 | const arm_cp15_start_section_config *section; |
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115 | |
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116 | section = &imx_mmu_config_table[ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX]; |
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117 | _Memory_Initialize( |
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118 | &_Memory_Areas[0], |
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119 | (void *) section->begin, |
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120 | (void *) section->end |
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121 | ); |
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122 | } |
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123 | |
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124 | RTEMS_SYSINIT_ITEM( |
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125 | bsp_memory_initialize, |
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126 | RTEMS_SYSINIT_MEMORY, |
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127 | RTEMS_SYSINIT_ORDER_MIDDLE |
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128 | ); |
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129 | |
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130 | static const Memory_Information _Memory_Information = |
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131 | MEMORY_INFORMATION_INITIALIZER(_Memory_Areas); |
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132 | |
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133 | const Memory_Information *_Memory_Get(void) |
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134 | { |
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135 | return &_Memory_Information; |
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136 | } |
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