1 | /* |
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2 | * Copyright (c) 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <bsp/bootcard.h> |
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17 | #include <bsp/fatal.h> |
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18 | #include <bsp/fdt.h> |
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19 | #include <bsp/irq-generic.h> |
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20 | #include <bsp/linker-symbols.h> |
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21 | #include <dev/clock/arm-generic-timer.h> |
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22 | #include <libcpu/arm-cp15.h> |
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23 | |
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24 | #include <libfdt.h> |
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25 | |
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26 | #define MAGIC_IRQ_OFFSET 32 |
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27 | |
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28 | void *imx_get_reg_of_node(const void *fdt, int node) |
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29 | { |
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30 | int len; |
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31 | const uint32_t *val; |
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32 | |
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33 | val = fdt_getprop(fdt, node, "reg", &len); |
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34 | if (val == NULL || len < 4) { |
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35 | return NULL; |
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36 | } |
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37 | |
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38 | return (void *) fdt32_to_cpu(val[0]); |
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39 | } |
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40 | |
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41 | rtems_vector_number imx_get_irq_of_node( |
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42 | const void *fdt, |
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43 | int node, |
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44 | size_t index |
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45 | ) |
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46 | { |
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47 | int len; |
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48 | const uint32_t *val; |
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49 | |
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50 | val = fdt_getprop(fdt, node, "interrupts", &len); |
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51 | if (val == NULL || len < (int) ((index + 1) * 12)) { |
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52 | return BSP_INTERRUPT_VECTOR_INVALID; |
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53 | } |
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54 | |
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55 | return fdt32_to_cpu(val[index * 3 + 1]) + MAGIC_IRQ_OFFSET; |
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56 | } |
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57 | |
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58 | uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) |
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59 | { |
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60 | return intr[1] + MAGIC_IRQ_OFFSET; |
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61 | } |
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62 | |
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63 | static bool imx_is_imx6(const void *fdt) |
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64 | { |
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65 | /* |
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66 | * At the moment: Check for some compatible strings that should be there |
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67 | * somewhere in every fdt. |
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68 | * |
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69 | * FIXME: It would be nice if some CPU-ID could be used instead. But I didn't |
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70 | * find one. |
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71 | */ |
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72 | int node; |
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73 | |
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74 | node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imx6ul"); |
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75 | if (node >= 0) { |
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76 | return true; |
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77 | } |
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78 | |
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79 | node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imx6ull"); |
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80 | if (node >= 0) { |
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81 | return true; |
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82 | } |
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83 | |
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84 | return false; |
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85 | } |
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86 | |
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87 | #define SYSCNT_CNTCR (0x0) |
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88 | #define SYSCNT_CNTCR_ENABLE (1 << 0) |
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89 | #define SYSCNT_CNTCR_HDBG (1 << 1) |
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90 | #define SYSCNT_CNTCR_FCREQ(n) (1 << (8 + (n))) |
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91 | #define SYSCNT_CNTFID(n) (0x20 + 4 * (n)) |
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92 | |
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93 | static uint32_t imx_syscnt_enable_and_return_frequency(const void *fdt) |
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94 | { |
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95 | uint32_t freq; |
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96 | volatile void *syscnt_base; |
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97 | |
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98 | /* That's not in the usual FDTs. Sorry for falling back to a magic value. */ |
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99 | if (imx_is_imx6(fdt)) { |
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100 | syscnt_base = (void *)0x021dc000; |
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101 | } else { |
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102 | syscnt_base = (void *)0x306c0000; |
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103 | } |
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104 | |
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105 | freq = *(uint32_t *)(syscnt_base + SYSCNT_CNTFID(0)); |
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106 | |
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107 | arm_cp15_set_counter_frequency(freq); |
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108 | |
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109 | *(uint32_t *)(syscnt_base + SYSCNT_CNTCR) = |
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110 | SYSCNT_CNTCR_ENABLE | |
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111 | SYSCNT_CNTCR_HDBG | |
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112 | SYSCNT_CNTCR_FCREQ(0); |
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113 | |
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114 | return freq; |
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115 | } |
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116 | |
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117 | void arm_generic_timer_get_config( |
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118 | uint32_t *frequency, |
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119 | uint32_t *irq |
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120 | ) |
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121 | { |
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122 | const void *fdt; |
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123 | int node; |
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124 | int len; |
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125 | const uint32_t *val; |
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126 | |
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127 | fdt = bsp_fdt_get(); |
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128 | node = fdt_path_offset(fdt, "/timer"); |
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129 | |
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130 | val = fdt_getprop(fdt, node, "clock-frequency", &len); |
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131 | if (val != NULL && len >= 4) { |
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132 | *frequency = fdt32_to_cpu(val[0]); |
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133 | } else { |
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134 | /* |
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135 | * Normally clock-frequency would be provided by the boot loader. If it |
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136 | * didn't add one, we have to initialize the system counter ourself. |
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137 | */ |
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138 | *frequency = imx_syscnt_enable_and_return_frequency(fdt); |
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139 | } |
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140 | |
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141 | /* FIXME: Figure out how Linux gets a proper IRQ number */ |
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142 | *irq = imx_get_irq_of_node(fdt, node, 0) - 16; |
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143 | } |
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144 | |
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145 | uintptr_t imx_gic_dist_base; |
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146 | |
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147 | static void imx_find_gic(const void *fdt) |
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148 | { |
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149 | int node; |
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150 | |
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151 | node = fdt_path_offset(fdt, "/interrupt-controller"); |
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152 | if (node < 0) { |
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153 | node = fdt_path_offset(fdt, "/soc/interrupt-controller"); |
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154 | } |
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155 | imx_gic_dist_base = (uintptr_t) imx_get_reg_of_node(fdt, node); |
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156 | |
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157 | #if defined(RTEMS_SMP) |
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158 | /* |
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159 | * Secondary processors start with a disabled data cache and use the GIC to |
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160 | * deterine if they can continue the initialization, see |
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161 | * arm_gic_irq_initialize_secondary_cpu(). |
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162 | */ |
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163 | rtems_cache_flush_multiple_data_lines( |
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164 | &imx_gic_dist_base, |
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165 | sizeof(imx_gic_dist_base) |
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166 | ); |
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167 | #endif |
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168 | } |
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169 | |
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170 | void bsp_start(void) |
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171 | { |
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172 | imx_find_gic(bsp_fdt_get()); |
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173 | bsp_interrupt_initialize(); |
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174 | rtems_cache_coherent_add_area( |
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175 | bsp_section_nocacheheap_begin, |
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176 | (uintptr_t) bsp_section_nocacheheap_size |
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177 | ); |
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178 | } |
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