1 | /* |
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2 | * Copyright (c) 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <bsp/fdt.h> |
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17 | #include <bsp/imx-gpio.h> |
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18 | #include <libfdt.h> |
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19 | #include <arm/freescale/imx/imx_ccmvar.h> |
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20 | #include <arm/freescale/imx/imx_ecspireg.h> |
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21 | #include <dev/spi/spi.h> |
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22 | #include <rtems/irq-extension.h> |
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23 | #include <sys/param.h> |
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24 | #include <sys/endian.h> |
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25 | |
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26 | #define IMX_ECSPI_FIFO_SIZE 64 |
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27 | #define IMX_ECSPI_MAX_CHIPSELECTS 4 |
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28 | #define IMX_ECSPI_CS_NONE IMX_ECSPI_MAX_CHIPSELECTS |
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29 | |
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30 | typedef struct imx_ecspi_bus imx_ecspi_bus; |
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31 | |
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32 | struct imx_ecspi_bus { |
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33 | spi_bus base; |
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34 | volatile imx_ecspi *regs; |
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35 | uint32_t conreg; |
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36 | uint32_t speed_hz; |
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37 | uint32_t mode; |
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38 | uint8_t bits_per_word; |
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39 | uint8_t cs; |
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40 | uint32_t msg_todo; |
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41 | const spi_ioc_transfer *msg; |
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42 | uint32_t todo; |
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43 | uint32_t in_transfer; |
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44 | uint8_t *rx_buf; |
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45 | const uint8_t *tx_buf; |
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46 | void (*push)(imx_ecspi_bus *, volatile imx_ecspi *); |
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47 | void (*pop)(imx_ecspi_bus *, volatile imx_ecspi *); |
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48 | rtems_id task_id; |
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49 | rtems_vector_number irq; |
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50 | struct { |
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51 | struct imx_gpio_pin pin; |
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52 | bool valid; |
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53 | } cspins[IMX_ECSPI_MAX_CHIPSELECTS]; |
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54 | }; |
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55 | |
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56 | static bool imx_ecspi_is_rx_fifo_not_empty(volatile imx_ecspi *regs) |
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57 | { |
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58 | return (regs->statreg & IMX_ECSPI_RR) != 0; |
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59 | } |
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60 | |
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61 | static void imx_ecspi_reset(volatile imx_ecspi *regs) |
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62 | { |
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63 | while (imx_ecspi_is_rx_fifo_not_empty(regs)) { |
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64 | regs->rxdata; |
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65 | } |
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66 | } |
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67 | |
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68 | static void imx_ecspi_done(imx_ecspi_bus *bus) |
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69 | { |
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70 | rtems_event_transient_send(bus->task_id); |
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71 | } |
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72 | |
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73 | #define IMC_ECSPI_PUSH(type) \ |
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74 | static void imx_ecspi_push_##type(imx_ecspi_bus *bus, volatile imx_ecspi *regs) \ |
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75 | { \ |
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76 | type val = 0; \ |
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77 | if (bus->tx_buf != NULL) { \ |
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78 | val = *(type *)bus->tx_buf; \ |
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79 | bus->tx_buf += sizeof(type); \ |
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80 | } \ |
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81 | bus->todo -= sizeof(type); \ |
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82 | regs->txdata = val; \ |
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83 | } |
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84 | |
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85 | #define IMX_ECSPI_POP(type) \ |
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86 | static void imx_ecspi_pop_##type(imx_ecspi_bus *bus, volatile imx_ecspi *regs) \ |
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87 | { \ |
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88 | uint32_t val = regs->rxdata; \ |
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89 | if (bus->rx_buf != NULL) { \ |
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90 | *(type *)bus->rx_buf = val; \ |
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91 | bus->rx_buf += sizeof(type); \ |
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92 | } \ |
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93 | } |
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94 | |
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95 | IMC_ECSPI_PUSH(uint8_t) |
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96 | IMX_ECSPI_POP(uint8_t) |
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97 | IMC_ECSPI_PUSH(uint16_t) |
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98 | IMX_ECSPI_POP(uint16_t) |
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99 | IMC_ECSPI_PUSH(uint32_t) |
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100 | IMX_ECSPI_POP(uint32_t) |
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101 | |
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102 | static void imx_ecspi_push_uint32_t_swap( |
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103 | imx_ecspi_bus *bus, |
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104 | volatile imx_ecspi *regs |
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105 | ) |
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106 | { |
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107 | uint32_t val = 0; |
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108 | |
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109 | if (bus->tx_buf != NULL) { |
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110 | val = bswap32(*(uint32_t *)bus->tx_buf); |
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111 | bus->tx_buf += sizeof(uint32_t); |
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112 | } |
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113 | |
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114 | bus->todo -= sizeof(uint32_t); |
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115 | regs->txdata = val; |
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116 | } |
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117 | |
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118 | static void imx_ecspi_pop_uint32_t_swap( |
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119 | imx_ecspi_bus *bus, |
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120 | volatile imx_ecspi *regs |
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121 | ) |
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122 | { |
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123 | uint32_t val = regs->rxdata; |
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124 | |
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125 | if (bus->rx_buf != NULL) { |
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126 | *(uint32_t *)bus->rx_buf = bswap32(val); |
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127 | bus->rx_buf += sizeof(uint32_t); |
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128 | } |
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129 | } |
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130 | |
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131 | static void imx_ecspi_push(imx_ecspi_bus *bus, volatile imx_ecspi *regs) |
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132 | { |
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133 | while (bus->todo > 0 && bus->in_transfer < IMX_ECSPI_FIFO_SIZE) { |
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134 | (*bus->push)(bus, regs); |
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135 | ++bus->in_transfer; |
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136 | } |
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137 | } |
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138 | |
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139 | /* Call with IMX_ECSPI_CS_NONE for @a cs to set all to idle */ |
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140 | static void |
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141 | imx_ecspi_set_chipsel(imx_ecspi_bus *bus, uint32_t cs) |
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142 | { |
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143 | size_t i; |
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144 | |
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145 | /* Currently this is fixed active low */ |
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146 | static const uint32_t idle = 1; |
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147 | static const uint32_t select = 0; |
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148 | |
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149 | for (i = 0; i < IMX_ECSPI_MAX_CHIPSELECTS; ++i) { |
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150 | if (bus->cspins[i].valid) { |
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151 | if (i != cs) { |
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152 | imx_gpio_set_output(&bus->cspins[i].pin, idle); |
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153 | } else { |
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154 | imx_gpio_set_output(&bus->cspins[cs].pin, select); |
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155 | } |
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156 | } |
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157 | } |
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158 | } |
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159 | |
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160 | static uint32_t imx_ecspi_conreg_divider(imx_ecspi_bus *bus, uint32_t speed_hz) |
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161 | { |
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162 | uint32_t post; |
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163 | uint32_t pre; |
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164 | uint32_t clk_in; |
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165 | |
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166 | clk_in = bus->base.max_speed_hz; |
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167 | |
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168 | if (clk_in > speed_hz) { |
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169 | post = fls((int) clk_in) - fls((int) speed_hz); |
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170 | |
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171 | if (clk_in > (speed_hz << post)) { |
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172 | ++post; |
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173 | } |
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174 | |
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175 | /* We have 2^4 == 16, use the pre-divider for this factor */ |
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176 | post = MAX(4, post) - 4; |
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177 | |
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178 | if (post <= 0xf) { |
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179 | pre = howmany(clk_in, speed_hz << post) - 1; |
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180 | } else { |
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181 | post = 0xf; |
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182 | pre = 0xf; |
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183 | } |
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184 | } else { |
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185 | post = 0; |
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186 | pre = 0; |
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187 | } |
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188 | |
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189 | return IMX_ECSPI_CONREG_POST_DIVIDER(post) |
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190 | | IMX_ECSPI_CONREG_PRE_DIVIDER(pre); |
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191 | } |
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192 | |
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193 | static void imx_ecspi_config( |
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194 | imx_ecspi_bus *bus, |
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195 | volatile imx_ecspi *regs, |
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196 | uint32_t speed_hz, |
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197 | uint8_t bits_per_word, |
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198 | uint32_t mode, |
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199 | uint8_t cs |
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200 | ) |
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201 | { |
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202 | uint32_t conreg; |
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203 | uint32_t testreg; |
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204 | uint32_t configreg; |
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205 | uint32_t dmareg; |
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206 | uint32_t cs_bit; |
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207 | |
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208 | conreg = IMX_ECSPI_CONREG_CHANNEL_MODE(0xf) |
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209 | | IMX_ECSPI_CONREG_SMC | IMX_ECSPI_CONREG_EN; |
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210 | testreg = regs->testreg; |
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211 | configreg = regs->configreg; |
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212 | dmareg = regs->dmareg; |
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213 | cs_bit = 1U << cs; |
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214 | |
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215 | conreg |= imx_ecspi_conreg_divider(bus, speed_hz); |
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216 | conreg |= IMX_ECSPI_CONREG_CHANNEL_SELECT(cs); |
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217 | |
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218 | configreg |= IMX_ECSPI_CONFIGREG_SS_CTL(cs_bit); |
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219 | |
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220 | if ((mode & SPI_CPHA) != 0) { |
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221 | configreg |= IMX_ECSPI_CONFIGREG_SCLK_PHA(cs_bit); |
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222 | } else { |
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223 | configreg &= ~IMX_ECSPI_CONFIGREG_SCLK_PHA(cs_bit); |
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224 | } |
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225 | |
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226 | if ((mode & SPI_CPOL) != 0) { |
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227 | configreg |= IMX_ECSPI_CONFIGREG_SCLK_POL(cs_bit); |
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228 | configreg |= IMX_ECSPI_CONFIGREG_SCLK_CTL(cs_bit); |
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229 | } else { |
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230 | configreg &= ~IMX_ECSPI_CONFIGREG_SCLK_POL(cs_bit); |
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231 | configreg &= ~IMX_ECSPI_CONFIGREG_SCLK_CTL(cs_bit); |
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232 | } |
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233 | |
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234 | if ((mode & SPI_CS_HIGH) != 0) { |
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235 | configreg |= IMX_ECSPI_CONFIGREG_SS_POL(cs_bit); |
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236 | } else { |
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237 | configreg &= ~IMX_ECSPI_CONFIGREG_SS_POL(cs_bit); |
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238 | } |
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239 | |
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240 | if ((mode & SPI_LOOP) != 0) { |
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241 | testreg |= IMX_ECSPI_TESTREG_LBC; |
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242 | } else { |
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243 | testreg &= ~IMX_ECSPI_TESTREG_LBC; |
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244 | } |
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245 | |
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246 | dmareg = IMX_ECSPI_DMAREG_TX_THRESHOLD_SET(dmareg, IMX_ECSPI_FIFO_SIZE/2); |
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247 | |
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248 | regs->conreg = conreg; |
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249 | regs->testreg = testreg; |
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250 | regs->dmareg = dmareg; |
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251 | regs->configreg = configreg; |
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252 | |
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253 | bus->conreg = conreg; |
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254 | bus->speed_hz = speed_hz; |
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255 | bus->bits_per_word = bits_per_word; |
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256 | bus->mode = mode; |
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257 | bus->cs = cs; |
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258 | |
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259 | /* FIXME: Clock change delay */ |
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260 | } |
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261 | |
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262 | static void imx_ecspi_set_push_pop( |
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263 | imx_ecspi_bus *bus, |
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264 | uint32_t len, |
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265 | uint8_t bits_per_word |
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266 | ) |
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267 | { |
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268 | uint32_t conreg; |
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269 | |
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270 | conreg = bus->conreg; |
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271 | |
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272 | if (len % 4 == 0 && len <= IMX_ECSPI_FIFO_SIZE) { |
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273 | conreg |= IMX_ECSPI_CONREG_BURST_LENGTH((len * 8) - 1); |
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274 | |
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275 | bus->push = imx_ecspi_push_uint32_t_swap; |
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276 | bus->pop = imx_ecspi_pop_uint32_t_swap; |
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277 | } else { |
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278 | conreg |= IMX_ECSPI_CONREG_BURST_LENGTH(bits_per_word - 1); |
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279 | |
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280 | if (bits_per_word <= 8) { |
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281 | bus->push = imx_ecspi_push_uint8_t; |
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282 | bus->pop = imx_ecspi_pop_uint8_t; |
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283 | } else if (bits_per_word <= 16) { |
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284 | bus->push = imx_ecspi_push_uint16_t; |
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285 | bus->pop = imx_ecspi_pop_uint16_t; |
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286 | } else { |
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287 | bus->push = imx_ecspi_push_uint32_t; |
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288 | bus->pop = imx_ecspi_pop_uint32_t; |
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289 | } |
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290 | } |
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291 | |
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292 | bus->regs->conreg = conreg; |
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293 | } |
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294 | |
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295 | static void imx_ecspi_next_msg(imx_ecspi_bus *bus, volatile imx_ecspi *regs) |
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296 | { |
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297 | if (bus->msg_todo > 0) { |
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298 | const spi_ioc_transfer *msg; |
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299 | |
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300 | msg = bus->msg; |
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301 | |
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302 | if ( |
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303 | msg->speed_hz != bus->speed_hz |
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304 | || msg->bits_per_word != bus->bits_per_word |
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305 | || msg->mode != bus->mode |
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306 | || msg->cs != bus->cs |
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307 | ) { |
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308 | imx_ecspi_config( |
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309 | bus, |
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310 | regs, |
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311 | msg->speed_hz, |
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312 | msg->bits_per_word, |
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313 | msg->mode, |
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314 | msg->cs |
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315 | ); |
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316 | } |
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317 | if ((msg->mode & SPI_NO_CS) != 0) { |
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318 | imx_ecspi_set_chipsel(bus, IMX_ECSPI_CS_NONE); |
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319 | } else { |
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320 | imx_ecspi_set_chipsel(bus, msg->cs); |
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321 | } |
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322 | |
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323 | bus->todo = msg->len; |
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324 | bus->rx_buf = msg->rx_buf; |
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325 | bus->tx_buf = msg->tx_buf; |
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326 | imx_ecspi_set_push_pop(bus, msg->len, msg->bits_per_word); |
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327 | imx_ecspi_push(bus, regs); |
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328 | regs->intreg = IMX_ECSPI_TE | IMX_ECSPI_TDR; |
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329 | } else { |
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330 | regs->intreg = 0; |
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331 | imx_ecspi_done(bus); |
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332 | } |
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333 | } |
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334 | |
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335 | static void imx_ecspi_interrupt(void *arg) |
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336 | { |
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337 | imx_ecspi_bus *bus; |
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338 | volatile imx_ecspi *regs; |
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339 | |
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340 | bus = arg; |
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341 | regs = bus->regs; |
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342 | |
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343 | while (imx_ecspi_is_rx_fifo_not_empty(regs)) { |
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344 | (*bus->pop)(bus, regs); |
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345 | --bus->in_transfer; |
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346 | } |
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347 | |
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348 | if (bus->todo > 0) { |
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349 | imx_ecspi_push(bus, regs); |
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350 | } else if (bus->in_transfer > 0) { |
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351 | regs->intreg = IMX_ECSPI_RR; |
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352 | } else { |
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353 | --bus->msg_todo; |
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354 | ++bus->msg; |
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355 | imx_ecspi_next_msg(bus, regs); |
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356 | } |
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357 | } |
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358 | |
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359 | static int imx_ecspi_check_messages( |
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360 | imx_ecspi_bus *bus, |
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361 | const spi_ioc_transfer *msg, |
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362 | uint32_t size) |
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363 | { |
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364 | while(size > 0) { |
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365 | if (msg->delay_usecs != 0) { |
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366 | return -EINVAL; |
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367 | } |
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368 | if (msg->bits_per_word > 32) { |
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369 | return -EINVAL; |
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370 | } |
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371 | if ((msg->mode & |
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372 | ~(SPI_CPHA | SPI_CPOL | SPI_LOOP | SPI_NO_CS)) != 0) { |
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373 | return -EINVAL; |
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374 | } |
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375 | if ((msg->mode & SPI_NO_CS) == 0 && |
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376 | (msg->cs > IMX_ECSPI_MAX_CHIPSELECTS || !bus->cspins[msg->cs].valid)) { |
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377 | return -EINVAL; |
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378 | } |
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379 | if (msg->cs_change != 0) { |
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380 | return -EINVAL; |
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381 | } |
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382 | |
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383 | ++msg; |
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384 | --size; |
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385 | } |
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386 | |
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387 | return 0; |
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388 | } |
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389 | |
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390 | static int imx_ecspi_transfer( |
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391 | spi_bus *base, |
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392 | const spi_ioc_transfer *msgs, |
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393 | uint32_t n |
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394 | ) |
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395 | { |
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396 | imx_ecspi_bus *bus; |
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397 | int rv; |
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398 | |
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399 | bus = (imx_ecspi_bus *) base; |
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400 | |
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401 | rv = imx_ecspi_check_messages(bus, msgs, n); |
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402 | |
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403 | if (rv == 0) { |
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404 | bus->msg_todo = n; |
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405 | bus->msg = &msgs[0]; |
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406 | bus->task_id = rtems_task_self(); |
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407 | |
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408 | imx_ecspi_next_msg(bus, bus->regs); |
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409 | rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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410 | imx_ecspi_set_chipsel(bus, IMX_ECSPI_CS_NONE); |
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411 | } |
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412 | return rv; |
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413 | } |
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414 | |
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415 | static void imx_ecspi_destroy(spi_bus *base) |
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416 | { |
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417 | imx_ecspi_bus *bus; |
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418 | |
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419 | bus = (imx_ecspi_bus *) base; |
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420 | rtems_interrupt_handler_remove(bus->irq, imx_ecspi_interrupt, bus); |
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421 | spi_bus_destroy_and_free(&bus->base); |
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422 | } |
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423 | |
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424 | static int imx_ecspi_init(imx_ecspi_bus *bus, const void *fdt, int node) |
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425 | { |
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426 | rtems_status_code sc; |
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427 | int len; |
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428 | const uint32_t *val; |
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429 | size_t i; |
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430 | |
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431 | for (i = 0; i < IMX_ECSPI_MAX_CHIPSELECTS; ++i) { |
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432 | rtems_status_code sc_gpio = imx_gpio_init_from_fdt_property( |
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433 | &bus->cspins[i].pin, node, "cs-gpios", IMX_GPIO_MODE_OUTPUT, i); |
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434 | bus->cspins[i].valid = (sc_gpio == RTEMS_SUCCESSFUL); |
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435 | } |
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436 | imx_ecspi_set_chipsel(bus, IMX_ECSPI_CS_NONE); |
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437 | |
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438 | imx_ecspi_config( |
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439 | bus, |
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440 | bus->regs, |
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441 | bus->base.max_speed_hz, |
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442 | 8, |
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443 | 0, |
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444 | 0 |
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445 | ); |
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446 | imx_ecspi_reset(bus->regs); |
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447 | |
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448 | sc = rtems_interrupt_handler_install( |
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449 | bus->irq, |
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450 | "ECSPI", |
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451 | RTEMS_INTERRUPT_UNIQUE, |
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452 | imx_ecspi_interrupt, |
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453 | bus |
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454 | ); |
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455 | if (sc != RTEMS_SUCCESSFUL) { |
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456 | return EAGAIN; |
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457 | } |
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458 | |
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459 | val = fdt_getprop(fdt, node, "pinctrl-0", &len); |
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460 | if (len == 4) { |
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461 | imx_iomux_configure_pins(fdt, fdt32_to_cpu(val[0])); |
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462 | } |
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463 | |
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464 | return 0; |
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465 | } |
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466 | |
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467 | static int imx_ecspi_setup(spi_bus *base) |
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468 | { |
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469 | imx_ecspi_bus *bus; |
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470 | |
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471 | bus = (imx_ecspi_bus *) base; |
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472 | |
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473 | if ( |
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474 | bus->base.speed_hz > imx_ccm_ipg_hz() |
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475 | || bus->base.bits_per_word > 32 |
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476 | ) { |
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477 | return -EINVAL; |
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478 | } |
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479 | |
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480 | imx_ecspi_config( |
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481 | bus, |
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482 | bus->regs, |
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483 | bus->base.speed_hz, |
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484 | bus->base.bits_per_word, |
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485 | bus->base.mode, |
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486 | bus->base.cs |
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487 | ); |
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488 | return 0; |
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489 | } |
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490 | |
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491 | int spi_bus_register_imx(const char *bus_path, const char *alias_or_path) |
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492 | { |
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493 | const void *fdt; |
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494 | const char *path; |
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495 | int node; |
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496 | imx_ecspi_bus *bus; |
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497 | int eno; |
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498 | |
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499 | fdt = bsp_fdt_get(); |
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500 | path = fdt_get_alias(fdt, alias_or_path); |
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501 | |
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502 | if (path == NULL) { |
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503 | path = alias_or_path; |
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504 | } |
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505 | |
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506 | node = fdt_path_offset(fdt, path); |
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507 | if (node < 0) { |
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508 | rtems_set_errno_and_return_minus_one(ENXIO); |
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509 | } |
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510 | |
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511 | bus = (imx_ecspi_bus *) spi_bus_alloc_and_init(sizeof(*bus)); |
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512 | if (bus == NULL){ |
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513 | return -1; |
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514 | } |
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515 | |
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516 | bus->base.max_speed_hz = imx_ccm_ecspi_hz(); |
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517 | bus->base.delay_usecs = 0; |
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518 | bus->regs = imx_get_reg_of_node(fdt, node); |
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519 | bus->irq = imx_get_irq_of_node(fdt, node, 0); |
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520 | |
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521 | eno = imx_ecspi_init(bus, fdt, node); |
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522 | if (eno != 0) { |
---|
523 | (*bus->base.destroy)(&bus->base); |
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524 | rtems_set_errno_and_return_minus_one(eno); |
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525 | } |
---|
526 | |
---|
527 | bus->base.transfer = imx_ecspi_transfer; |
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528 | bus->base.destroy = imx_ecspi_destroy; |
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529 | bus->base.setup = imx_ecspi_setup; |
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530 | |
---|
531 | return spi_bus_register(&bus->base, bus_path); |
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532 | } |
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