source: rtems/bsps/arm/imx/include/arm/freescale/imx/imx_srcreg.h @ d7d66d7

5
Last change on this file since d7d66d7 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*
2 * Copyright (c) 2017 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef IMX_SRCREG_H
16#define IMX_SRCREG_H
17
18#include <bsp/utility.h>
19
20typedef struct {
21        uint32_t scr;
22#define IMX_SRC_SCR_DOM_EN BSP_BIT32(31)
23#define IMX_SRC_SCR_LOCK BSP_BIT32(30)
24#define IMX_SRC_SCR_DOMAIN3 BSP_BIT32(27)
25#define IMX_SRC_SCR_DOMAIN2 BSP_BIT32(26)
26#define IMX_SRC_SCR_DOMAIN1 BSP_BIT32(25)
27#define IMX_SRC_SCR_DOMAIN0 BSP_BIT32(24)
28#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET(val) BSP_FLD32(val, 4, 7)
29#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_GET(reg) BSP_FLD32GET(reg, 4, 7)
30#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
31        uint32_t a7rcr0;
32#define IMX_SRC_A7RCR0_DOM_EN BSP_BIT32(31)
33#define IMX_SRC_A7RCR0_LOCK BSP_BIT32(30)
34#define IMX_SRC_A7RCR0_DOMAIN3 BSP_BIT32(27)
35#define IMX_SRC_A7RCR0_DOMAIN2 BSP_BIT32(26)
36#define IMX_SRC_A7RCR0_DOMAIN1 BSP_BIT32(25)
37#define IMX_SRC_A7RCR0_DOMAIN0 BSP_BIT32(24)
38#define IMX_SRC_A7RCR0_A7_L2RESET BSP_BIT32(21)
39#define IMX_SRC_A7RCR0_A7_SOC_DBG_RESET BSP_BIT32(20)
40#define IMX_SRC_A7RCR0_MASK_WDOG1_RST(val) BSP_FLD32(val, 16, 19)
41#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_GET(reg) BSP_FLD32GET(reg, 16, 19)
42#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
43#define IMX_SRC_A7RCR0_A7_ETM_RESET1 BSP_BIT32(13)
44#define IMX_SRC_A7RCR0_A7_ETM_RESET0 BSP_BIT32(12)
45#define IMX_SRC_A7RCR0_A7_DBG_RESET1 BSP_BIT32(9)
46#define IMX_SRC_A7RCR0_A7_DBG_RESET0 BSP_BIT32(8)
47#define IMX_SRC_A7RCR0_A7_CORE_RESET1 BSP_BIT32(5)
48#define IMX_SRC_A7RCR0_A7_CORE_RESET0 BSP_BIT32(4)
49#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET1 BSP_BIT32(1)
50#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET0 BSP_BIT32(0)
51        uint32_t a7rcr1;
52#define IMX_SRC_A7RCR1_DOM_EN BSP_BIT32(31)
53#define IMX_SRC_A7RCR1_LOCK BSP_BIT32(30)
54#define IMX_SRC_A7RCR1_DOMAIN3 BSP_BIT32(27)
55#define IMX_SRC_A7RCR1_DOMAIN2 BSP_BIT32(26)
56#define IMX_SRC_A7RCR1_DOMAIN1 BSP_BIT32(25)
57#define IMX_SRC_A7RCR1_DOMAIN0 BSP_BIT32(24)
58#define IMX_SRC_A7RCR1_A7_CORE1_ENABLE BSP_BIT32(1)
59        uint32_t m4rcr;
60#define IMX_SRC_M4RCR_DOM_EN BSP_BIT32(31)
61#define IMX_SRC_M4RCR_LOCK BSP_BIT32(30)
62#define IMX_SRC_M4RCR_DOMAIN3 BSP_BIT32(27)
63#define IMX_SRC_M4RCR_DOMAIN2 BSP_BIT32(26)
64#define IMX_SRC_M4RCR_DOMAIN1 BSP_BIT32(25)
65#define IMX_SRC_M4RCR_DOMAIN0 BSP_BIT32(24)
66#define IMX_SRC_M4RCR_WDOG3_RST_OPTION BSP_BIT32(9)
67#define IMX_SRC_M4RCR_WDOG3_RST_OPTION_M4 BSP_BIT32(8)
68#define IMX_SRC_M4RCR_MASK_WDOG3_RST(val) BSP_FLD32(val, 4, 7)
69#define IMX_SRC_M4RCR_MASK_WDOG3_RST_GET(reg) BSP_FLD32GET(reg, 4, 7)
70#define IMX_SRC_M4RCR_MASK_WDOG3_RST_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
71#define IMX_SRC_M4RCR_ENABLE_M4 BSP_BIT32(3)
72#define IMX_SRC_M4RCR_SW_M4P_RST BSP_BIT32(2)
73#define IMX_SRC_M4RCR_SW_M4C_RST BSP_BIT32(1)
74#define IMX_SRC_M4RCR_SW_M4C_NON_SCLR_RST BSP_BIT32(0)
75        uint32_t reserved_10;
76        uint32_t ercr;
77        uint32_t reserved_18;
78        uint32_t hsicphy_rcr;
79        uint32_t usbophy1_rcr;
80        uint32_t usbophy2_rcr;
81        uint32_t mipiphy_rcr;
82        uint32_t pciephy_rcr;
83        uint32_t reserved_30[10];
84        uint32_t sbmr1;
85        uint32_t srsr;
86        uint32_t reserved_60[2];
87        uint32_t sisr;
88        uint32_t simr;
89        uint32_t sbmr2;
90        uint32_t gpr1;
91        uint32_t gpr2;
92        uint32_t gpr3;
93        uint32_t gpr4;
94        uint32_t gpr5;
95        uint32_t gpr6;
96        uint32_t gpr7;
97        uint32_t gpr8;
98        uint32_t gpr9;
99        uint32_t gpr10;
100        uint32_t reserved_9c[985];
101        uint32_t ddrc_rcr;
102} imx_src;
103
104#endif /* IMX_SRCREG_H */
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