source: rtems/bsps/arm/imx/include/arm/freescale/imx/imx_i2creg.h

Last change on this file was bcef89f2, checked in by Sebastian Huber <sebastian.huber@…>, on 05/19/23 at 06:18:25

Update company name

The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.

  • Property mode set to 100644
File size: 2.7 KB
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2017 embedded brains GmbH & Co. KG
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef IMX_I2CREG_H
29#define IMX_I2CREG_H
30
31#include <bsp/utility.h>
32
33typedef struct {
34        uint16_t iadr;
35#define IMX_I2C_IADR_ADR(val) BSP_FLD16(val, 1, 7)
36#define IMX_I2C_IADR_ADR_GET(reg) BSP_FLD16GET(reg, 1, 7)
37#define IMX_I2C_IADR_ADR_SET(reg, val) BSP_FLD16SET(reg, val, 1, 7)
38        uint16_t reserved_02;
39        uint16_t ifdr;
40#define IMX_I2C_IFDR_IC(val) BSP_FLD16(val, 0, 5)
41#define IMX_I2C_IFDR_IC_GET(reg) BSP_FLD16GET(reg, 0, 5)
42#define IMX_I2C_IFDR_IC_SET(reg, val) BSP_FLD16SET(reg, val, 0, 5)
43        uint16_t reserved_06;
44        uint16_t i2cr;
45#define IMX_I2C_I2CR_IEN BSP_BIT16(7)
46#define IMX_I2C_I2CR_IIEN BSP_BIT16(6)
47#define IMX_I2C_I2CR_MSTA BSP_BIT16(5)
48#define IMX_I2C_I2CR_MTX BSP_BIT16(4)
49#define IMX_I2C_I2CR_TXAK BSP_BIT16(3)
50#define IMX_I2C_I2CR_RSTA BSP_BIT16(2)
51        uint16_t reserved_0a;
52        uint16_t i2sr;
53#define IMX_I2C_I2SR_ICF BSP_BIT16(7)
54#define IMX_I2C_I2SR_IAAS BSP_BIT16(6)
55#define IMX_I2C_I2SR_IBB BSP_BIT16(5)
56#define IMX_I2C_I2SR_IAL BSP_BIT16(4)
57#define IMX_I2C_I2SR_SRW BSP_BIT16(2)
58#define IMX_I2C_I2SR_IIF BSP_BIT16(1)
59#define IMX_I2C_I2SR_RXAK BSP_BIT16(0)
60        uint16_t reserved_0e;
61        uint16_t i2dr;
62#define IMX_I2C_I2DR_DATA(val) BSP_FLD16(val, 0, 7)
63#define IMX_I2C_I2DR_DATA_GET(reg) BSP_FLD16GET(reg, 0, 7)
64#define IMX_I2C_I2DR_DATA_SET(reg, val) BSP_FLD16SET(reg, val, 0, 7)
65} imx_i2c;
66
67#endif /* IMX_I2CREG_H */
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